The TPD5S115 device is an integrated HDMI companion chip solution. The device provides a regulated 5-V output (5VOUT) for sourcing the HDMI power line. The regulated 5-V output supplies up to 55 mA to the HDMI receiver with a current limiting function. The TPD5S115 features two control signals: EN and LS_OE. The control of 5VOUT and the hot plug detect (HPD) circuitry is independent of the LS_OE control signal and is controlled by the EN pin. The EN pin allows the detection scheme (5VOUT + HPD) to be active before turning on the whole HDMI link. The LS_OE activates the internal LDO, CEC, SCL, and SDA buffers only when EN is also activated. This dual stage enable scheme ensures optimized power saving for portable applications.
There are three noninverting, bidirectional, voltage level translation circuits for the SDA, SCL, and CEC lines. Each have a common power rail (VCCA) on the A side from 1.1 V to 3.6 V. On the B side, the SCL_B and SDA_B each have an internal 1.75-kΩ pullup connected to the regulated 5-V rail (5VOUT). The DDC (SCL_B and SDA_B) pins meet the I2C specification and drive up to 750-pF loads with the buffers. The CEC_B pin has an internal 27-kΩ pullup to an internal 3.3-V supply. The TPD5S115 exceeds the IEC61000-4-2 (Level 4) ESD protection level. This device features a space saving, 1.72-mm × 1.72-mm, YFF package with 0.4-mm pitch.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPD5S115 | DSBGA (16) | 1.72 mm × 1.72 mm |
Changes from C Revision (December 2016) to D Revision
Changes from B Revision (March 2013) to C Revision
Changes from A Revision (February 2013) to B Revision
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
5VOUT | C1 | O | DC-DC output. The 5-V power pin can supply a 55-mA regulated current to the HDMI receiver. A separate DC-DC converter control pin (EN) disables the DC-DC converter when operating at low-power mode |
CEC_A | D3 | I/O | LS system side CEC bus I/O. This pin is bidirectional and referenced to VCCA |
CEC_B | B1 | I/O | LS HDMI connector side CEC bus I/O. This pin is bidirectional and referenced to the 3.3-V internal supply |
EN | C3 | C | DC-DC enable. Enables the DC-DC converter and HPD circuitry when EN is HIGH. The EN is referenced based off VCCA |
GND | A2 | G | Device ground |
HPD_A | B4 | O | System side output for the hot plug detect. This pin is unidirectional and is referenced to VCCA |
HPD_B | A3 | I | HDMI side input for the hot plug detect. This pin is unidirectional and is referenced to 5VOUT |
LS_OE | B3 | C | Level shifter enable. This pin is referenced to VCCA. Enables level shifters and LDO when EN is HIGH and LS_OE is HIGH |
PGND | D1 | G | DC-DC converter ground. These pins are isolated from the GND pins. This pin should be tied to system GND |
SCL_A, SDA_A | D4, C4 | I/O | LS system side input and output for I2C Bus. These pins are bidirectional and referenced to VCCA |
SCL_B, SDA_B | A1, B2 | I/O | LS HDMI side connector side input and output for I2C Bus. These pins are bidirectional and referenced to 5VOUT |
SW | C2 | I | Switch input. This pin is the inductor input for the DC-DC converter |
VBAT | D2 | P | Battery supply. This voltage is typically 2.3 V to 5.5 V |
VCCA | A4 | P | System side supply. This voltage is typically 1.2 V to 3.3 V from the core microcontroller |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | VCCA | 4 | V | |
VBAT | –0.3 | 6 | V | |
Input voltage, VI(2) | SCL_A, SDA_A, CEC_A | –0.3 | 4 | V |
SCL_B, SDA_B, CEC_B, HPD_B | –0.3 | 6 | ||
EN, LS_OE | –0.3 | 4 | ||
Voltage applied to any output in the high-impedance or power‑off state, VO(2) | SCL_A, SDA_A, CEC_A | –0.3 | 4 | V |
SCL_B, SDA_B, CEC_B | –0.3 | 6 | ||
Voltage applied to any output in the high or low state, VO(2) | SCL_A, SDA_A, CEC_A | –0.3 | VCCA + 0.3 | V |
SCL_B, SDA_B, CEC_B | –0.3 | 5VOUT + 0.3 | ||
Input clamp current (IV < 0) | –50 | mA | ||
Output clamp current (VO < 0) | –50 | mA | ||
Continuous current through 5VOUT, or GND | ±100 | mA | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | All pins except pins 4A, B3, C3, C4, D3, and D4 | 500 | V |
Pins 4A, B3, C3, C4, D3, and D4 | 2000 | ||||
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | 1000 | ||||
IEC 61000-4-2 Contact Discharge | Pins A1, A3, B1, B2, and C1 | ±14000 | |||
IEC 61000-4-2 Air-gap Discharge | Pins A1, A3, B1, B2, and C1 | ±16000 |
MIN | NOM | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
VCCA | Supply voltage, VCCA | 1.2 | 3.6 | V | |||
VBAT | Supply voltage, VBAT | 2.3 | 5.5 | V | |||
VIH | High-level input voltage | VCCA = 1.2 V to 3.6 V | SCL_A, SDA_A | 0.7 × VCCA | VCCA | V | |
CEC_A | 0.7 × VCCA | VCCA | |||||
EN, LS_OE | 1 | VCCA | |||||
5VOUT = 5 V | SCL_B, SDA_B | 0.7 × 5VOUT | 5VOUT | ||||
CEC_B | 0.7 × 3.3 V (internal)(1) | 3.3 V (internal)(1) | |||||
HPD_B | 2 | ||||||
VIL | Low-Level input voltage | VCCA = 1.2 V to 3.6 V | SCL_A, SDA_A | –0.5 | 0.082 × VCCA | V | |
CEC_A | –0.5 | 0.082 × VCCA | |||||
EN, LS_OE | –0.5 | 0.4 | |||||
5VOUT = 5 V | SCL_B, SDA_B | –0.5 | 0.3 × 5VOUT | ||||
CEC_B | –0.5 | 0.3 × 3.3 (internal)(1) | |||||
HPD_B | 0 | 0.8 | |||||
VILC | Low-level input voltage | –0.5 | 0.065 × VCCA | V | |||
VOL – VILC | Delta between VOL and VILC (VIO = 2.5 V) | 0.1 × VCCA | V | ||||
TA | Operating free-air temperature | –40 | 85 | °C |
THERMAL METRIC(1) | TPD5S115 | UNIT | |
---|---|---|---|
YFF (DSBGA) | |||
16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 78.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 0.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 13.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 2.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 13 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOHA | IOH = –10 µA, VI = VIH, VCCA = 1.2 V to 3.6 V | VCCA × 0.8 | V | ||||
VOLA | IOL = 10 µA, VI = VIL, VCCA = 1.2 V to 3.6 V | VCCA × 0.16 | V | ||||
VOHB | IOH = –10 µA, VI = VIH | V | |||||
VOLB | IOL = 3 mA, VI = VIL | 0.4 | V | ||||
RPU | Internal pullup | SCL_A, SDA_A | Pullup connected to VCCA rail | 10 | kΩ | ||
SCL_B, SDA_B | Pullup connected to 5-V rail | 1.75 | |||||
IPULLUPAC | Transient boosted pullup current (rise-time accelerator) |
SCL_B, SDA_B | Pullup connected to 5-V rail | 15 | mA | ||
IOFF | Leakage current | A port | VCCA = 0 V, VI or VO = 0 to 3.6 V, VCCA = 0 V | ±5 | µA | ||
B port | 5VOUT = 0 V, VI or VO = 0 to 5.5 V, VCCA = 0 V to 3.6 V | ±5 | |||||
IOZ | A port | VO = VCCO or GND, VCCA = 1.2 V to 3.6 V | ±5 | ||||
B port | VI = VCCI or GND, VCCA = 1.2 V to 3.6 V | ±5 | |||||
CL | Bus load capacitance | A port | 15 | pF | |||
B port | 750 | ||||||
SUPPLY CURRENT | |||||||
ICCA | VCCA supply current | Standby | I/Os = HIGH | 2 | µA | ||
Active | I/Os = HIGH | 15 | µA | ||||
ICCB | VBAT supply current | Standby | EN = LOW, LS_OE = LOW | 0.5 | µA | ||
DC-DC and HPD active |
EN = HIGH, LS_OE = LOW | 30 | 50 | µA | |||
DC-DC, HPD, DDC, CEC Active | EN = HIGH, LS_OE = LOW, I/Os = HIGH | 225 | 300 | µA | |||
DC-DC CONVERTER | |||||||
VBAT | Input voltage | 2.3 | 5.5 | V | |||
VOUT | Total DC output voltage(1) | 4.9 | 5 | 5.13 | V | ||
TOVA | Total output voltage accuracy(2) | 4.8 | 5 | 5.3 | V | ||
VIO_Ripple | Output voltage ripple, loaded | IO = 65 mA | 50.6 | mVPP | |||
IO = 150 mA | 16 | ||||||
fCLK | Internal operating frequency | VBAT = 2.3 V to 5.5 V | 3.5 | MHz | |||
tSTART | Start-up time | From EN input to 5-V power output 90% point | 187 | µs | |||
IO | Output current | VBAT = 2.3 V to 5.5 V | 55 | mA | |||
Reverse leakage current, VO | EN = LOW, VO = 5.5 V | 2.5 | µA | ||||
Leakage current from battery to VO | EN = LOW | 5 | µA | ||||
VBATUV | Undervoltage lockout threshold | Falling | 2 | V | |||
Rising | 2.1 | V | |||||
Line transient response | VBAT = 3.4 V, IO = 20 mA to 65 mA, A 217 Hz, 600 mVPP square wave pulse |
17.1 | mVpk | ||||
Load transient response | VBAT = 3.4 V, IO = 5 mA to 65 mA, 10-µs pulse, tRISE = tFALL = 0.1 µs |
63.5 | mVpk | ||||
IINRUSH | Inrush current, average over tSTART | VBAT = 2.3 V to 5.5 V, IOUT = 65 mA | 168 | mA | |||
ISC | Short-circuit current limit from output | 90 | mA | ||||
VOLTAGE LEVEL SHIFTER CEC LINE (x_A & x_B PORTS) | |||||||
VOHA | IOH = –10 µA, VI = VIH, VCCA = 1.2 V to 3.6 V | VCCA × 0.8 | V | ||||
VOLA | IOL = 10 µA, VI = VIL, VCCA = 1.2 V to 3.6 V | VCCA × 0.16 | V | ||||
VOHB | IOH = –20 µA, VI = VIH | VCCA × 0.8 | V | ||||
VOLB | IOL = 3 mA, VI = VIL | 0.4 | V | ||||
RPU | Internal pullup | CEC_A | Pullup connected to VCCA rail | 10 | kΩ | ||
CEC_B | Pullup connected to 3.3 V rail | 22 | 26 | 30 | |||
RPD | Internal pulldown | CEC_B | Pullup connected to GND | 14 | MΩ | ||
IOFF | A port | VCCA = 0 V, VI or VO = 0 to 3.6 V, VCCA = 0 V | ±5 | µA | |||
B port | 5VOUT = 0 V, VI or VO = 0 to 5.5 V, VCCA = 0 V to 3.6 V | ±1.8 | |||||
IOZ | A port | VO = VCCO or GND, VCCA = 1.2 V to 3.6 V | ±5 | ||||
B port | VI = VCCI or GND, VCCA = 1.2 V to 3.6 V | ±5 | |||||
VOLTAGE LEVEL SHIFTER - HPD LINE (X_A & x_B) | |||||||
VOHA | IOH = –3 mA, VI = VIH, VCCA = 1.2 V to 3.6 V | VCCA × 0.7 | V | ||||
VOLA | IOL = 3 mA, VI = VIL, VCCA = 1.2 V to 3.6 V | 0.4 | V | ||||
RPD | Internal pulldown | HPD_B | Pullup connected to GND | 100 | kΩ | ||
IOZ | A port | VI = VCCI or GND, VCCA = 3.6 V | ±5 | µA | |||
LS_OE, EN | |||||||
II | VI = VCCA or GND, VCCA = 1.2 V to 3.6 V | ±12 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Capacitance | EN, LS_OE | VBIAS = 1.8 V, f = 1 MHz, 30-mVPP AC signal |
VCCA = 3.6 V, VBAT = 5 V | 7.1 | 9.5 | pF | |
SCL_A, SDA_A, CEC_A | VCCA = 3.6 V, VBAT = 5 V, EN = LOW | 7 | pF | ||||
HPD_A, HPD_B | VCCA = 3.6 V, VBAT = 5 V, EN = LOW | 4 | pF | ||||
SCL_B, SDA_B | VBIAS = 2.5 V, f = 100 kHz, 3.5-VPP AC signal |
VCCA = 3.6 V, VBAT = 5 V, EN = LOW, LS_OE = HIGH | 10 | pF | |||
CEC_B | VBIAS = 1.65 V, f = 100 kHz, 2.5-VPP AC signal |
VCCA = 3.6 V, VBAT = 5 V, EN = LOW, LS_OE = HIGH | 7 | pF | |||
CEC_B | VCCA = 0 V, 5V_IN = 0 V | 7 | pF |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SCL and SDA LINES (x_A & x_B PORTS) | |||||||
tPHL | High-to-low propagation delay | A to B | DDC channels enabled | 394 | ns | ||
B to A | DDC channels enabled | 347 | |||||
tPLH | Low-to-high propagation delay | A to B | DDC channels enabled | 504 | ns | ||
B to A | DDC channels enabled | 171 | |||||
tFALL | Fall time | A port | DDC channels enabled | 146 | ns | ||
B port | DCC channels enabled | 135 | |||||
tRISE | Rise time | A port | DCC channels enabled | 190 | ns | ||
B port | DCC channels enabled | 93 | |||||
fMAX | Maximum switching frequency | DCC channels enabled | 400 | kHz | |||
CEC LINE (x_A & x_B PORTS) | |||||||
tPHL | High-to-low propagation delay | A to B | CEC channels enabled | 550 | ns | ||
B to A | CEC channels enabled | 350 | |||||
tPLH | Low-to-high propagation delay | A to B | CEC channels enabled | 13 | µs | ||
B to A | CEC channels enabled | 290 | ns | ||||
tFALL | Fall time | A port | CEC channels enabled | 146 | ns | ||
B port | CEC channels enabled | 200 | |||||
tRISE | Rise time | A port | CEC channels enabled | 190 | ns | ||
B port | CEC channels enabled | 16.4 | µs | ||||
HPD LINE (x_A & x_B PORTS) | |||||||
tPHL | Propagation delay | B to A | CEC channels enabled | 10.4 | ns | ||
tPLH | Low-to-high propagation delay | B to A | CEC channels enabled | 9.9 | ns | ||
tFALL | Fall time | A port | CEC channels enabled | 0.7 | ns | ||
tRISE | Rise time | A port | CEC channels enabled | 0.8 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SCL, SDA LINES (x_A & x_B PORTS) | |||||||
tPHL | High-to-low propagation delay | A to B | DDC channels enabled | 375 | ns | ||
B to A | DDC channels enabled | 272 | |||||
tPLH | Low-to-high propagation delay | A to B | DDC channels enabled | 488 | ns | ||
B to A | DDC channels enabled | 166 | |||||
tFALL | Fall time | A port | DDC channels enabled | 114 | ns | ||
B port | DCC channels enabled | 135 | |||||
tRISE | Rise time | A port | DCC channels enabled | 186 | ns | ||
B port | DCC channels enabled | 93 | |||||
fMAX | Maximum switching frequency | DCC channels enabled | 400 | kHz | |||
CEC Line (x_A & x_B Ports) | |||||||
tPHL | High-to-low propagation delay | A to B | CEC channels enabled | 536 | ns | ||
B to A | CEC channels enabled | 272 | |||||
tPLH | Low-to-high propagation delay | A to B | CEC channels enabled | 13 | µs | ||
B to A | CEC channels enabled | 285 | ns | ||||
tFALL | Fall time | A port | CEC channels enabled | 113 | ns | ||
B port | CEC channels enabled | 201 | |||||
tRISE | Rise time | A port | CEC channels enabled | 187 | ns | ||
B port | CEC channels enabled | 16 | µs | ||||
HPD LINE (x_A & x_B PORTS) | |||||||
tPHL | High-to-low propagation delay | B to A | CEC channels enabled | 10 | ns | ||
tPLH | Low-to-high propagation delay | B to A | CEC channels enabled | 10 | ns | ||
tFALL | Fall time | A port | CEC channels enabled | 0.46 | ns | ||
tRISE | Rise time | A port | CEC channels enabled | 0.5 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SCL, SDA LINES (x_A & x_B PORTS) | |||||||
tPHL | High-to-low propagation delay | A to B | DDC channels enabled | 370 | ns | ||
B to A | DDC channels enabled | 230 | |||||
tPLH | Low-to-high propagation delay | A to B | DDC channels enabled | 480 | ns | ||
B to A | DDC channels enabled | 163 | |||||
tFALL | Fall time | A port | DDC channels enabled | 100 | ns | ||
B port | DCC channels enabled | 135 | |||||
tRISE | Rise time | A port | DCC channels enabled | 180 | ns | ||
B port | DCC channels enabled | 93 | |||||
fMAX | Maximum switching frequency | DCC channels enabled | 400 | kHz | |||
CEC LINE (x_A & x_B PORTS) | |||||||
tPHL | High-to-low propagation delay | A to B | CEC channels enabled | 530 | ns | ||
B to A | CEC channels enabled | 230 | |||||
tPLH | Low-to-high propagation delay | A to B | CEC channels enabled | 13 | µs | ||
B to A | CEC channels enabled | 280 | ns | ||||
tFALL | Fall time | A port | CEC channels enabled | 98 | ns | ||
B port | CEC channels enabled | 200 | |||||
tRISE | Rise time | A port | CEC channels enabled | 180 | ns | ||
B port | CEC channels enabled | 16 | µs | ||||
HPD LINE (x_A & x_B PORTS) | |||||||
tPHL | High-to-low propagation delay | B to A | CEC channels enabled | 10 | ns | ||
tPLH | Low-to-high propagation delay | B to A | CEC channels enabled | 10 | ns | ||
tFALL | Fall time | A port | CEC channels enabled | 0.41 | ns | ||
tRISE | Rise time | A port | CEC channels enabled | 0.41 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SCL, SDA LINES (x_A & x_B PORTS) | |||||||
tPHL | High-to-low propagation delay | A to B | DDC channels enabled | 370 | ns | ||
B to A | DDC channels enabled | 185 | |||||
tPLH | Low-to-high propagation delay | A to B | DDC channels enabled | 467 | ns | ||
B to A | DDC channels enabled | 160 | |||||
tFALL | Fall time | A port | DDC channels enabled | 80 | ns | ||
B port | DCC channels enabled | 135 | |||||
tRISE | Rise time | A port | DCC channels enabled | 179 | ns | ||
B port | DCC channels enabled | 93 | |||||
fMAX | Maximum switching frequency | DCC channels enabled | 400 | kHz | |||
CEC LINE (x_A & x_B PORTS) | |||||||
tPHL | High-to-low propagation delay | A to B | CEC channels enabled | 530 | ns | ||
B to A | CEC channels enabled | 185 | |||||
tPLH | Low-to-high propagation delay | A to B | CEC channels enabled | 13 | µs | ||
B to A | CEC channels enabled | 275 | ns | ||||
tFALL | Fall time | A port | CEC channels enabled | 80 | ns | ||
B port | CEC channels enabled | 200 | |||||
tRISE | Rise time | A port | CEC channels enabled | 180 | ns | ||
B port | CEC channels enabled | 16 | µs | ||||
HPD LINE (x_A & x_B PORTS) | |||||||
tPHL | High-to-low propagation delay | B to A | CEC channels enabled | 10 | ns | ||
tPLH | Low-to-high propagation delay | B to A | CEC channels enabled | 10 | ns | ||
tFALL | Fall time | A port | CEC channels enabled | 0.35 | ns | ||
tRISE | Rise time | A port | CEC channels enabled | 0.35 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SCL, SDA LINES (x_A & x_B PORTS) | |||||||
tPHL | High-to-low propagation delay | A to B | DDC channels enabled | 370 | ns | ||
B to A | DDC channels enabled | 160 | |||||
tPLH | Low-to-high propagation delay | A to B | DDC channels enabled | 460 | ns | ||
B to A | DDC channels enabled | 155 | |||||
tFALL | Fall time | A port | DDC channels enabled | 75 | ns | ||
B port | DCC channels enabled | 135 | |||||
tRISE | Rise time | A port | DCC channels enabled | 180 | ns | ||
B port | DCC channels enabled | 93 | |||||
fMAX | Maximum switching frequency | DCC channels enabled | 400 | kHz | |||
CEC LINE (x_A & x_B PORTS) | |||||||
tPHL | High-to-low propagation delay | A to B | CEC channels enabled | 530 | ns | ||
B to A | CEC channels enabled | 160 | |||||
tPLH | Low-to-high propagation delay | A to B | CEC channels enabled | 13 | µs | ||
B to A | CEC channels enabled | 275 | ns | ||||
tFALL | Fall time | A port | CEC channels enabled | 73 | ns | ||
B port | CEC channels enabled | 200 | |||||
tRISE | Rise time | A port | CEC channels enabled | 180 | ns | ||
B port | CEC channels enabled | 16 | µs | ||||
HPD LINE (x_A & x_B PORTS) | |||||||
tPHL | High-to-low propagation delay | B to A | CEC channels enabled | 10 | ns | ||
tPLH | Low-to-high propagation delay | B to A | CEC channels enabled | 10 | ns | ||
tFALL | Fall time | A port | CEC channels enabled | 0.34 | ns | ||
tRISE | Rise time | A port | CEC channels enabled | 0.36 | ns |