SLVSBL2D October   2012  – June 2017 TPD5S115

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics - I/O Capacitances
    7. 6.7  Switching Characteristics - VCCA = 1.2 V
    8. 6.8  Switching Characteristics - VCCA = 1.5 V
    9. 6.9  Switching Characteristics - VCCA = 1.8 V
    10. 6.10 Switching Characteristics - VCCA = 2.5 V
    11. 6.11 Switching Characteristics - VCCA = 3.3 V
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Rise-Time Accelerators
      2. 7.3.2 Hot Plug Detect
      3. 7.3.3 CEC Level Shift Operation
      4. 7.3.4 Pullup Resistor
      5. 7.3.5 Undervoltage Lockout
      6. 7.3.6 Soft Start
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Save Mode
      2. 7.4.2 Enable
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 DDC or CEC Level Shifter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 DDC or CEC Level Shifter Operational Notes for VCCA = 1.8 V
          2. 8.2.1.2.2 Input Capacitor
          3. 8.2.1.2.3 Output Capacitor
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Other Application Circuits
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

For proper operation, follow these layout and design guidelines:

  • Place the TPD5S115 as close to the connector as possible. This allows it to remove the energy associated with ESD strike before it reaches the internal circuitry of the system board.
  • Place power line capacitors and inductors close to the pins with wide traces to allow enough current to flow through with less trace parasitics. Ensure that there is enough metallization for the GND pad. A sufficient current path enables safe discharge of all the energy associated with the ESD strike.

10.2 Layout Example

TPD5S115 layout.gif Figure 17. Board Layout With DC-DC Components (Top View)