JAJSFN1 June   2018 TPD6S300A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     CCおよびSBUの過電圧保護
    2.     CCおよびDP/DMの過電圧保護
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings—JEDEC Specification
    3. 8.3 ESD Ratings—IEC Specification
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Thermal Information
    6. 8.6 Electrical Characteristics
    7. 8.7 Timing Requirements
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins or CC1, CC2, DP, DM Pins): 24-VDC Tolerant
      2. 9.3.2 6-Channels of IEC 61000-4-2 ESD Protection (CC1, CC2, SBU1, SBU2, DP, DM Pins)
      3. 9.3.3 CC1, CC2 Overvoltage Protection FETs 600 mA Capable for Passing VCONN Power
      4. 9.3.4 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
      5. 9.3.5 Advantages over TPD6S300
        1. 9.3.5.1 Improved Dead Battery Performance
        2. 9.3.5.2 USB Type-C Port Stays Connected during an IEC 61000-4-2 ESD Strike
      6. 9.3.6 3-mm × 3-mm WQFN Package
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 VBIAS Capacitor Selection
        2. 10.2.2.2 Dead Battery Operation
        3. 10.2.2.3 CC Line Capacitance
        4. 10.2.2.4 Additional ESD Protection on CC and SBU Lines
        5. 10.2.2.5 FLT Pin Operation
        6. 10.2.2.6 How to Connect Unused Pins
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins or CC1, CC2, DP, DM Pins): 24-VDC Tolerant

The TPD6S300A provides 4-channels of Short-to-VBUS Overvoltage Protection for the CC1, CC2, SBU1, and SBU2 pins (or the CC1, CC2, DP, and DM pins) of the USB Type-C connector. The TPD6S300A is able to handle 24-VDC on its C_CC1, C_CC2, C_SBU1, and C_SBU2 pins. This is necessary because according to the USB PD specification, with VBUS set for 20-V operation, the VBUS voltage is allowed to legally swing up to 21 V and 21.5 V on voltage transitions from a different USB PD VBUS voltage. The TPD6S300A builds in tolerance up to 24-VBUS to provide margin above this 21.5-V specification to be able to support USB PD adaptors that may break the USB PD specification.

When a short-to-VBUS event occurs, ringing happens due to the RLC elements in the hot-plug event. With very low resistance in this RLC circuit, ringing up to twice the settling voltage can appear on the connector. More than 2x ringing can be generated if any capacitor on the line derates in capacitance value during the short-to-VBUS event. This means that more than 44 V could be seen on a USB Type-C pin during a Short-to-VBUS event. The TPD6S300A has built in circuit protection to handle this ringing. The diode clamps used for IEC ESD protection also clamp the ringing voltage during the short-to-VBUS event to limit the peak ringing to approximately 30 V. Additionally, the overvoltage protection FETs integrated inside the TPD6S300A are 30-V tolerant, therefore being capable of supporting the high-voltage ringing waveform that is experienced during the short-to-VBUS event. The well designed combination of voltage clamps and 30-V tolerant OVP FETs insures the TPD6S300A can handle Short-to-VBUS hot-plug events with hot-plug voltages as high as 24-VDC.

The TPD6S300A has an extremely fast turnoff time of 70 ns typical. Furthermore, additional voltage clamps are placed after the OVP FET on the system side (CC1, CC2, SBU1, SBU2) pins of the TPD6S300A, to further limit the voltage and current that are exposed to the USB Type-C CC/PD controller during the 70 ns interval while the OVP FET is turning off. The combination of connector side voltage clamps, OVP FETs with extremely fast turnoff time, and system side voltage clamps all work together to insure the level of stress seen on a CC1, CC2, SBU1, or SBU2 pin during a short-to-VBUS event is less than or equal to an HBM event. This is done by design, as any USB Type-C CC/PD controller will have built in HBM ESD protection.

The SBU OVP FETs where designed with a 1-GHz bandwidth to be able to be used to protect the DP, DM (USB2.0) pins in addition to the SBU pins. Some systems designers also prefer to protect the DP, DM pins from Short-to-VBUS events due to the potential for moisture/water in the connector to short the VBUS pins to DP, DM pins. This can be especially applicable in cases where the end equipment with a USB Type-C connector is trying to be made water-proof. If desiring to protect the DP, DM pins on the USB Type-C connector from a Short-to-VBUS event, connect the C_SBUx pins to the DP, DM pins on the USB Type-C connector, and the SBUx pins to the USB2.0 pins of the system device being protected from the Short-to-VBUS event.

Figure 29 is an example of the TPD6S300A successfully protecting the TPS65982, the world's first fully integrated, full-featured USB Type-C and PD controller.

TPD6S300A TPD8S300_TPS6598x_STBUS.gifFigure 29. TPD6S300A Protecting the TPS65982 During a Short-to-VBUS Event