JAJSCP7 November   2016 TPL0401A-10-Q1 , TPL0401B-10-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Voltage Divider Mode
    5. 9.5 Programming
      1. 9.5.1 I2C General Operation and Overview
        1. 9.5.1.1 START and STOP Conditions
        2. 9.5.1.2 Data Validity and Byte Formation
        3. 9.5.1.3 Acknowledge (ACK) and Not Acknowledge (NACK)
        4. 9.5.1.4 Repeated Start
      2. 9.5.2 Programing With I2C
        1. 9.5.2.1 Write Operation
        2. 9.5.2.2 Read Operation
    6. 9.6 Register Maps
      1. 9.6.1 Slave Address
      2. 9.6.2 Register Address
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power Sequence
    2. 11.2 Power-On Reset Requirements
    3. 11.3 I2C Communication After Power Up
    4. 11.4 Wiper Position While Unpowered and After Power Up
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Application and Implementation

10.1 Application Information

There are many applications in which voltage division is needed through the use of a digital potentiometer such as the TPL0401x-10-Q1; this is one example of the many. In conjunction with many amplifiers, the TPL0401x-10-Q1 can effectively be used in voltage divider mode to create a buffer to adjust the reference voltage for DDR3 DIMM1 Memory.

10.2 Typical Application

TPL0401A-10-Q1 TPL0401B-10-Q1 App_Schem_SLIS182.gif Figure 20. DDR3 Voltage Reference Adjustment

10.2.1 Design Requirements

Table 3 lists the design parameters for this example.

Table 3. Design Parameters

PARAMETER EXAMPLE VALUE
Input voltage 1.5 V
VREF 0 V to 0.75 V

10.2.2 Detailed Design Procedure

The TPL0401x-10-Q1 can be used in voltage divider mode with a unity-gain op amp buffer to provide a clean voltage reference for DDR3 DIMM1 Memory. The analog output voltage, VREF1 is determined by the wiper setting programmed through the I2C bus.

The op amp is required to buffer the high-impedance output of the TPL0401x-10-Q1 or else loading placed on the output of the voltage divider affects the output voltage.

10.2.3 Application Curve

The voltage, 1.5 V, applied to terminal H of TPL0401x-10-Q1 determines the voltage that is buffered by the unity-gain op amp and divided as the DDR3 DIMM1 voltage reference. By using the TPL0401x-10-Q1, and dividing the 1.5 V, a maximum of 0.75 V is applied to the buffer and passed to the voltage divider. The output voltage then ranges from 0 V to 0.75 V.

TPL0401A-10-Q1 TPL0401B-10-Q1 D050_SLIS144.gif Figure 21. TPL0401-10-Q1 Digital Input vs Reference Voltage for DDR3 DIMM Memory