JAJSE10A May   2017  – May 2018 TPL7407LA

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      単純なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Inductive Load Drive
      2. 8.4.2 Resistive Load Drive
      3. 8.4.3 ON State Input Current
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unipolar Stepper Motor Driver
      2. 9.1.2 Multi-Purpose Sink Driver
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 TTL and other Logic Inputs
        2. 9.2.2.2 Input RC Snubber
        3. 9.2.2.3 High-Impedance Input Drivers
        4. 9.2.2.4 Drive Current
        5. 9.2.2.5 Output Low Voltage
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Improving Package Thermal Performance
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Power Supply Recommendations

The COM pin is the power supply pin of this device to power the gate drive circuitry. While a bypass capacitor on this pin is recommended for sensitive power supplies, it is not required for proper operation of the device. The COM pin supply ensures full drive potential with any GPIO above 1.5 V. The gate drive circuitry is based on low voltage CMOS transistors that can only handle a max gate voltage of 7 V. An integrated LDO reduces the COM voltage of 6.5 V to 30 V to a regulated voltage of 5.3 V. Though 6.5 V minimum is recommended for Vcom, the part still functions with a reduced COM voltage that has a reduced gate drive voltage and a resulting higher Rdson.