JAJSOQ2
December 2023
TPS1200-Q1
ADVANCE INFORMATION
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
7.3.2
Capacitive Load Driving Using FET Gate (PU, PD) Slew Rate Control
7.3.3
Short-Circuit Protection
7.3.3.1
Short-Circuit Protection With Auto-Retry
7.3.3.2
Short-Circuit Protection With Latch-Off
7.3.4
Overvoltage (OV) and Undervoltage Protection (UVLO)
7.3.5
Reverse Polarity Protection
7.3.6
Short-Circuit Protection Diagnosis (SCP_TEST)
7.3.7
TPS12000-Q1 as a Simple Gate Driver
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.1.1
Application Limitations
8.1.1.1
Short-Circuit Protection Delay
8.1.1.2
Short-Circuit Protection Threshold
8.2
Typical Application: Driving Power at all Times (PAAT) Loads
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
ドキュメントの更新通知を受け取る方法
9.2
サポート・リソース
9.3
Trademarks
9.4
静電気放電に関する注意事項
9.5
用語集
10
Revision History
11
Mechanical, Packaging, and Orderable Information
11.1
Tape and Reel Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DGX|19
MPSS147
サーマルパッド・メカニカル・データ
発注情報
jajsoq2_oa
6
Parameter Measurement Information
Figure 6-1
Timing Waveforms