JAJSND1D July   2022  – April 2024 TPS1211-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
      2. 8.3.2 Capacitive Load Driving
        1. 8.3.2.1 FET Gate Slew Rate Control
        2. 8.3.2.2 Using Precharge FET - (with TPS12111-Q1 Only)
      3. 8.3.3 Overcurrent and Short-Circuit Protection
        1. 8.3.3.1 Overcurrent Protection with Auto-Retry
        2. 8.3.3.2 Overcurrent Protection with Latch-Off
        3. 8.3.3.3 Short-Circuit Protection
      4. 8.3.4 Analog Current Monitor Output (IMON)
      5. 8.3.5 Overvoltage (OV) and Undervoltage Protection (UVLO)
      6. 8.3.6 Remote Temperature Sensing and Protection (DIODE)
      7. 8.3.7 Output Reverse Polarity Protection
      8. 8.3.8 TPS1211x-Q1 as a Simple Gate Driver
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Driving Zonal Controller Loads on 12-V Line in Power Distribution Unit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application: Reverse Polarity Protection with TPS12110-Q1
      1. 9.3.1 Design Requirements
      2. 9.3.2 External Component Selection
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.3.1 Overcurrent Protection with Auto-Retry

The CTMR programs the over current protection delay (tOC) and auto-retry time (tRETRY). Once the voltage across CS+ and CS– exceeds the set point, the CTMR starts charging with 82-µA pullup current. After the CTMR charges up to V(TMR_FLT), FLT_I asserts low providing warning on impending FET turn OFF. After CTMR charges to V(TMR_OC), PD pulls low to SRC turning OFF the FET. Post this event, the auto-retry behavior starts. The CTMR capacitor starts discharging with 2.5-uA pulldown current. After the voltage reaches V(TMR_LOW) level, the capacitor starts charging with 2.5-uA pullup. After 32 charging, discharging cycles of CTMR the FET turns ON back and FLT_I de-asserts after de-assertion delay of 260 µs.

Use Equation 7 to calculate the CTMR capacitor to be connected between TMR and GND.

Equation 7. C T M R = I T M R   ×   t O C 1.2

Where, ITMR is internal pull-up current of 82-µA, tOC is desired overcurrent response time.

Use Equation 8 to calculate the TFLT duration.

Equation 8. T F L T = 1.1   ×   C T M R 82   μ

Where, TFLT is the FLT_I assertion delay.

The auto-retry time can be computed as, tRETRY = 22.7 × 106 × CTMR.

If the overcurrent pulse duration is below tOC, then the FET remains ON and CTMR gets discharged using internal pulldown switch.

TPS1211-Q1 Overcurrent Protection with Auto-Retry Figure 8-10 Overcurrent Protection with Auto-Retry