JAJSOU3 March   2024 TPS1213-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, BST, SRC)
      2. 7.3.2 Capacitive Load Driving
        1. 7.3.2.1 Using Low Power Bypass FET (G2 drive) for Load Capacitor Charging
        2. 7.3.2.2 Using Main FET's (G1 drive) Gate Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Device Functional Modes
        1. 7.3.4.1 State Diagram
        2. 7.3.4.2 State Transition Timing Diagram
        3. 7.3.4.3 Power Down
        4. 7.3.4.4 Shutdown Mode
        5. 7.3.4.5 Low Power Mode
        6. 7.3.4.6 Active Mode
      5. 7.3.5 Undervoltage Protection (UVLO)
      6. 7.3.6 Reverse Polarity Protection
      7. 7.3.7 Short-Circuit Protection Diagnosis (SCP_TEST)
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Application Limitations
        1. 8.1.1.1 Short-Circuit Protection Delay
        2. 8.1.1.2 Short-Circuit Protection and Load wakeup Threshold
    2. 8.2 Typical Application 1: Driving Power at all times (PAAT) Loads With Automatic Load Wakeup
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application 2: Driving Power at all times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
      1. 8.3.1 Design Requirements
      2. 8.3.2 External Component Selection
      3. 8.3.3 Application Curves
    4. 8.4 TIDA-020065: Automotive Smart Fuse Reference Design driving Power at all times (PAAT) Loads With Automatic Load Wakeup, Output Bulk Capacitor Charging, Bi-directional Current Sensing and Software I2t
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.2.2 Using Main FET's (G1 drive) Gate Slew Rate Control

In the applications where low power bypass path is not used, the cap charging can be done using main FET gate drive control.

For limiting inrush current during turn-ON of the main FET with capacitive loads, use R1, R2, C1 as shown in Figure 7-6. The R1 and C1 components slow down the voltage ramp rate at the gate of main FET. The FET source follows the gate voltage resulting in a controlled voltage ramp across the output capacitors.

TPS1213-Q1 Inrush Current LimitingFigure 7-6 Inrush Current Limiting

Use the Equation 24 to calculate the inrush current during turn-ON of the FET.

Equation 5. IINRUSH= CLOAD× VBATTTcharge
Equation 6. C1= 0.63 × V(BST - SRC) × CLOADR1 × IINRUSH

Where,

CLOAD is the load capacitance.

VBATT is the input voltage and Tcharge is the charge time.

V(BST-SRC) is the charge pump voltage (11 V),

Use a damping resistor R2 (~ 10 Ω) in series with C1. Equation 6 can be used to compute required C1 value for a target inrush current. A 100kΩ resistor for R1 can be a good starting point for calculations.

Connecting G1PD pin of TPS12130-Q1 directly to the gate of the external FET ensures fast turn-OFF without any impact of R1 and C1 components.

C1 results in an additional loading on CBST to charge during turn-ON. Use below equation to calculate the required CBST value:

Equation 7. CBST = Qg(total)∆VBST+ 10 × C1

Where,

Qg(total) is the total gate charge of the FET,

ΔVBST (1 V typical) is the ripple voltage across BST to SRC pins.