JAJSOU3 March 2024 TPS1213-Q1
ADVANCE INFORMATION
In application designs with current sense configurations as shown in Figure 7-7 and Figure 7-8 with CTMR = Open, the short-circuit protection delay during power up with output short circuited does not match the specified maximum value of 10µs.
Testing has shown that the actual short-circuit protection delay during power up by EN/UVLO signal is approximately 70 µs. This increase in protection delay still allows for the TPS12130-Q1 to operate as designed, but results in larger power dissipation in the external MOSFET during output short-circuit scenario.
A design fix must be included in the final version of the IC.