JAJSOU3 March   2024 TPS1213-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, BST, SRC)
      2. 7.3.2 Capacitive Load Driving
        1. 7.3.2.1 Using Low Power Bypass FET (G2 drive) for Load Capacitor Charging
        2. 7.3.2.2 Using Main FET's (G1 drive) Gate Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Device Functional Modes
        1. 7.3.4.1 State Diagram
        2. 7.3.4.2 State Transition Timing Diagram
        3. 7.3.4.3 Power Down
        4. 7.3.4.4 Shutdown Mode
        5. 7.3.4.5 Low Power Mode
        6. 7.3.4.6 Active Mode
      5. 7.3.5 Undervoltage Protection (UVLO)
      6. 7.3.6 Reverse Polarity Protection
      7. 7.3.7 Short-Circuit Protection Diagnosis (SCP_TEST)
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Application Limitations
        1. 8.1.1.1 Short-Circuit Protection Delay
        2. 8.1.1.2 Short-Circuit Protection and Load wakeup Threshold
    2. 8.2 Typical Application 1: Driving Power at all times (PAAT) Loads With Automatic Load Wakeup
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application 2: Driving Power at all times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
      1. 8.3.1 Design Requirements
      2. 8.3.2 External Component Selection
      3. 8.3.3 Application Curves
    4. 8.4 TIDA-020065: Automotive Smart Fuse Reference Design driving Power at all times (PAAT) Loads With Automatic Load Wakeup, Output Bulk Capacitor Charging, Bi-directional Current Sensing and Software I2t
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

TPS1213-Q1 DGX Package, 19-Pin VSSOP (Top View)Figure 4-1 DGX Package, 19-Pin VSSOP (Top View)
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
EN/UVLO1I

EN/UVLO input. A voltage on this pin above V(ENR) enables normal operation. If EN/UVLO is below V(ENF) then gate drives are turned OFF and FLT asserts low.

Forcing this pin below V(ENF) (0.3V) shuts down the device reducing quiescent current. Optionally connect to the input supply through a resistive divider to set the undervoltage lockout.

When EN/UVLO is left floating an internal pulldown of 100nA pulls EN/UVLO low and keeps the device in OFF state.
LPM2I

Low power mode input. When driven high, the devices enter into active mode. When driven low, the devices enter into low power mode.

LPM has an internal weak pull down of 100nA to GND to keep G2 high when LPM is left floating.

INP3I

Input signal for external FET control. CMOS compatible input reference to GND that sets the state of G1PD and G1PU pins.

INP has an internal weak pull down of 100nA to GND to keep G1PD pulled to SRC when INP is left floating.

WAKE4OOpen drain wake output. This pin asserts low when the device enters into active mode (when LPM is driven high or when a load wake up event has occurred).
FLT5OOpen drain fault output. This pin asserts low during short circuit fault, charge pump UVLO, input UVLO and during SCP comparator diagnosis. If FLT feature is not desired then connect it to GND.
GND6GConnect GND to system ground.
CS_SEL7—

Reserved for future use. Connect to GND.

ISCP/LWU8I

Short circuit detection and load wakeup threshold setting.

SCP control for G1 during active mode (LPM = high) and load wakeup control on G2 during low power mode (LPM = low).

TMR9IFault timer input. A capacitor across TMR pin to GND sets the times for fault turnoff. Leave it open for fastest setting (< 10µs). Connect ISCP/LWU and TMR pin to GND to disable overcurrent protection.
SCP_TEST10I

Internal short circuit comparator (SCP) diagnosis input.

When SCP_TEST is driven low to high with INP pulled high, the internal SCP comparator operation is checked. FLT goes low and G1PD gets pulled to SRC if SCP comparator is functional.

Connect SCP_TEST pin to GND if this feature is not desired.

SCP_TEST has an internal weak pull down of 100nA to GND.

G211O

Low power mode FET gate drive output. It has 165 µA pullup and 2 A sink capacity

BST12OHigh side bootstrapped supply. An external capacitor with a minimum value of > Qg(tot) of the external FET must be connected between this pin and SRC.
SRC13OSource connection of the external FET.
G1PD14OHigh current gate driver pulldown. This pin pulls down to SRC. For the fastest turnoff, tie this pin directly to the gate of the external high side MOSFET.
G1PU15OHigh current gate driver pullup. This pin pulls up to BST. Connect this pin to G1PD for maximum gate drive transition speed. A resistor can be connected between this pin and the gate of the external MOSFET to control the in-rush current during turnon.
CS–17ICurrent sense negative input.
CS+18ICurrent sense positive input.
N.C19—

No connect.

VS20PSupply pin of the controller.
(1) I = input, O = output, I/O = input and output, P = power, G = ground