SLUSFA1A September   2024  – December 2024 TPS1214-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump and Gate Driver Output (VS, GATE, BST, SRC)
      2. 8.3.2 Capacitive Load Driving
        1. 8.3.2.1 Using Low Power Bypass FET (G Drive) for Load Capacitor Charging
        2. 8.3.2.2 Using Main FET (GATE drive) Gate Slew Rate Control
      3. 8.3.3 Overcurrent and Short-Circuit Protection
        1. 8.3.3.1 I2t-Based Overcurrent Protection
          1. 8.3.3.1.1 I2t-Based Overcurrent Protection With Auto-Retry
          2. 8.3.3.1.2 I2t-Based Overcurrent Protection With Latch-Off
        2. 8.3.3.2 Short-Circuit Protection
      4. 8.3.4 Analog Current Monitor Output (IMON)
      5. 8.3.5 NTC-Based Temperature Sensing (TMP) and Analog Monitor Output (ITMPO)
      6. 8.3.6 Fault Indication and Diagnosis (FLT, SCP_TEST)
      7. 8.3.7 Reverse Polarity Protection
      8. 8.3.8 Undervoltage Protection (UVLO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 State Transition Timing Diagram
      3. 8.4.3 Power Down
      4. 8.4.4 Shutdown Mode
      5. 8.4.5 Low Power Mode (LPM)
      6. 8.4.6 Active Mode (AM)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application 1: Driving Power at all times (PAAT) Loads With Automatic Load Wakeup
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application 2: Driving Power at all times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
      1. 9.3.1 Design Requirements
      2. 9.3.2 External Component Selection
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
8.3.3.1.1 I2t-Based Overcurrent Protection With Auto-Retry

The CI2t programs the over current protection delay (tOC_MIN) and CTMR programs auto-retry time (tRETRY). Once the voltage across CS1+ and CS1– exceeds the set point (V(OCP)), the CI2t capacitor starts charging with current proportional to ILOAD2 – IOC2 current.

After CI2t charges to V(I2t_OC), GATE pulls low to SRC turning OFF the main FET and FLT assets low as same time. Post this event, the auto-retry behavior starts. The CTMR starts charging with 2.5µA pullup current till voltage reaches V(TMR_HIGH) level. After this level, capacitor starts discharging with 2.5µA pulldown current.

After the voltage reaches V(TMR_LOW) level, the capacitor starts charging again with 2.5µA pullup. After 32 charging-discharging cycles of CTMR the FET turns ON back and FLT de-asserts.

TPS1214-Q1 I2t-Based Overcurrent Protection With Auto-RetryFigure 8-9 I2t-Based Overcurrent Protection With Auto-Retry

The auto-retry time can be set by CTMR capacitor to be connected across TMR and GND pins as per Equation 13.

Equation 13. t R E T R Y   ( s ) =   64   ×   C T M R   ×   V ( T M R _ H I G H )   -   V ( T M R _ L O W ) I ( T M R _ S R C )  

where

V(TMR_HIGH) is 1.2V (typ) and V(TMR_LOW) is 0.2V (typ)

I(TMR_SRC) is internal source current on TMR pin with 2.5µA (typ) value