SLUSFA1A September   2024  – December 2024 TPS1214-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump and Gate Driver Output (VS, GATE, BST, SRC)
      2. 8.3.2 Capacitive Load Driving
        1. 8.3.2.1 Using Low Power Bypass FET (G Drive) for Load Capacitor Charging
        2. 8.3.2.2 Using Main FET (GATE drive) Gate Slew Rate Control
      3. 8.3.3 Overcurrent and Short-Circuit Protection
        1. 8.3.3.1 I2t-Based Overcurrent Protection
          1. 8.3.3.1.1 I2t-Based Overcurrent Protection With Auto-Retry
          2. 8.3.3.1.2 I2t-Based Overcurrent Protection With Latch-Off
        2. 8.3.3.2 Short-Circuit Protection
      4. 8.3.4 Analog Current Monitor Output (IMON)
      5. 8.3.5 NTC-Based Temperature Sensing (TMP) and Analog Monitor Output (ITMPO)
      6. 8.3.6 Fault Indication and Diagnosis (FLT, SCP_TEST)
      7. 8.3.7 Reverse Polarity Protection
      8. 8.3.8 Undervoltage Protection (UVLO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 State Transition Timing Diagram
      3. 8.4.3 Power Down
      4. 8.4.4 Shutdown Mode
      5. 8.4.5 Low Power Mode (LPM)
      6. 8.4.6 Active Mode (AM)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application 1: Driving Power at all times (PAAT) Loads With Automatic Load Wakeup
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application 2: Driving Power at all times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
      1. 9.3.1 Design Requirements
      2. 9.3.2 External Component Selection
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.2.1 Using Low Power Bypass FET (G Drive) for Load Capacitor Charging

In high-current applications where several FETs are connected in parallel in main path, the gate slew rate control for the main FETs is not recommended due to unequal distribution of inrush currents among the FETs resulting in over sizing of the FETs.

The TPS1214-Q1 integrates pre-charge gate driver (G) with a dedicated control input (LPM) and bypass comparator between CS2+ and CS2– pins. This feature can be used to drive a separate low power bypass FET and pre-charge the capacitive load with inrush current limiting. Figure 8-4 shows the low power bypass FET implementation for capacitive load charging using TPS1214-Q1. An external capacitor Cg reduces the gate turn ON slew rate and controls the inrush current.

TPS1214-Q1 Capacitor Charging Using Gate (G) Slew Rate Control of Low Power Bypass FETFigure 8-4 Capacitor Charging Using Gate (G) Slew Rate Control of Low Power Bypass FET

During power-up with EN/UVLO pulled high and LPM pulled low, the device turns ON bypass FET (G drive) by pulling G high with 100μA of source current and the main path (GATE) is kept OFF.

In this low power mode (LPM), TPS1214-Q1 senses voltage between CS2+ and CS2– pins along with VGS of bypass FET (G to SRC). The voltage across CS2+ and CS2– is compared initially with V(LPM_SCP) threshold (2V typical) to detect powerup into short fault event until V(G_GOOD) threshold is reached.

After V(G_GOOD) threshold is reached, the voltage between CS2+ and CS2– is compared against V(LWU) threshold (200mV typ) for load wakeup event. With this scheme capacitor charging current (IINRUSH) can be set at higher than load wakeup threshold (ILWU) and power-up into short event can also be detected reliably as shown in below timing diagram:

TPS1214-Q1 Timing Diagram for Bulk Capacitor Charging Using Bypass Path Figure 8-5 Timing Diagram for Bulk Capacitor Charging Using Bypass Path

Setting the Load Wakeup Trigger Threshold:

During normal operation, the series resistor RBYPASS is used to set load wakeup current threshold. After VG_GOOD threshold is reached, the voltage between CS2+ and CS2– is compared against V(LWU) threshold (200mV typ) for load wakeup event.

RBYPASS can be selected using below equation:

Equation 2. R B Y P A S S   =   V (L W U) I L W U

Setting the INRUSH Current:

Use Equation 6 to calculate the IINRUSH:

Equation 3. IINRUSH= CLOAD× VBATTTcharge

Where,

CLOAD is the load capacitance.

VBATT is the input voltage and Tcharge is the charge time.

IINRUSH should be always less than wakeup in short in low power mode (ILPM_SC) current which can be calculated using following equation:

Equation 4. I L P M _ S C   =   V (L P M _ S C P) R B Y P A S S

Use Equation 5 to calculate the required Cg value.

Equation 5. Cg = CLOAD × I(G)IINRUSH

Where,

I(G) is 100µA (typical),

A series resistor Rg must be used in conjunction with Cg to limit the discharge current from Cg during turn-off. The recommended value for Rg is between 220Ω to 470Ω.

After the output capacitor is charged, main FETs can be controlled (GATE drive) and bypass FET (G drive) can be turned OFF by driving LPM high externally. The main FETs (G drive) can now be turned ON by driving INP high.

Figure 8-6 shows application circuit to charge large output capacitors using low power bypass path in high current applications.

TPS1214-Q1 TPS1214-Q1 Application Circuit for Capacitive Load Driving Using Low Power Bypass FET (Q3) and Series Resistor (RBYPASS) Figure 8-6 TPS1214-Q1 Application Circuit for Capacitive Load Driving Using Low Power Bypass FET (Q3) and Series Resistor (RBYPASS)