SLUSFA1A September   2024  – December 2024 TPS1214-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump and Gate Driver Output (VS, GATE, BST, SRC)
      2. 8.3.2 Capacitive Load Driving
        1. 8.3.2.1 Using Low Power Bypass FET (G Drive) for Load Capacitor Charging
        2. 8.3.2.2 Using Main FET (GATE drive) Gate Slew Rate Control
      3. 8.3.3 Overcurrent and Short-Circuit Protection
        1. 8.3.3.1 I2t-Based Overcurrent Protection
          1. 8.3.3.1.1 I2t-Based Overcurrent Protection With Auto-Retry
          2. 8.3.3.1.2 I2t-Based Overcurrent Protection With Latch-Off
        2. 8.3.3.2 Short-Circuit Protection
      4. 8.3.4 Analog Current Monitor Output (IMON)
      5. 8.3.5 NTC-Based Temperature Sensing (TMP) and Analog Monitor Output (ITMPO)
      6. 8.3.6 Fault Indication and Diagnosis (FLT, SCP_TEST)
      7. 8.3.7 Reverse Polarity Protection
      8. 8.3.8 Undervoltage Protection (UVLO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 State Transition Timing Diagram
      3. 8.4.3 Power Down
      4. 8.4.4 Shutdown Mode
      5. 8.4.5 Low Power Mode (LPM)
      6. 8.4.6 Active Mode (AM)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application 1: Driving Power at all times (PAAT) Loads With Automatic Load Wakeup
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application 2: Driving Power at all times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
      1. 9.3.1 Design Requirements
      2. 9.3.2 External Component Selection
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
8.3.3.1.2 I2t-Based Overcurrent Protection With Latch-Off

Connect 100kΩ resistor across TMR pin to GND for latch-off configuration.

Latch is reset on falling edge of INP or LPM going low or EN/UVLO (below V(ENF)) or power cycle VS below V(VS_PORF). At low edge, the timer counter is reset and CTMR is discharged. GATE pulls up to BST when INP is pulled high.

TPS1214-Q1 I2t-Based Overcurrent Protection With Latch-OffFigure 8-10 I2t-Based Overcurrent Protection With Latch-Off