SLVSHA1 September   2024 TPS1685

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Logic Interface
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Undervoltage Protection
      2. 7.3.2  Insertion Delay
      3. 7.3.3  Overvoltage Protection
      4. 7.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 7.3.4.1 Slew rate (dVdt) and Inrush Current Control
          1. 7.3.4.1.1 Start-Up Time Out
        2. 7.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 7.3.4.3 Active Current Limiting During Start-Up
        4. 7.3.4.4 Short-Circuit Protection
      5. 7.3.5  Analog Load Current Monitor (IMON)
      6. 7.3.6  Mode Selection (MODE)
      7. 7.3.7  Parallel Device Synchronization (SWEN)
      8. 7.3.8  Stacking Multiple eFuses for Unlimited Scalability
        1. 7.3.8.1 Current Balancing During Start-Up
      9. 7.3.9  Analog Junction Temperature Monitor (TEMP)
      10. 7.3.10 Overtemperature Protection
      11. 7.3.11 Fault Response and Indication (FLT)
      12. 7.3.12 Power Good Indication (PG)
      13. 7.3.13 Output Discharge
      14. 7.3.14 FET Health Monitoring
      15. 7.3.15 Single Point Failure Mitigation
        1. 7.3.15.1 IMON Pin Single Point Failure
        2. 7.3.15.2 IREF Pin Single Point Failure
        3. 7.3.15.3 ITIMER Pin Single Point Failure
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Single Device, Standalone Operation
      2. 8.1.2 Multiple Devices, Parallel Connection
    2. 8.2 Typical Application: 54V Power Path Protection in Data Center Servers
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Transient Protection
      2. 8.3.2 Output Short-Circuit Measurements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
  • VMA|27
サーマルパッド・メカニカル・データ
発注情報

Detailed Design Procedure

  • Determining the number of eFuse devices to be used in parallel

    By factoring in a small variation in the junction to ambient thermal resistance (RθJA), a single TPS1685x eFuse is rated at a maximum steady state DC current of 20A with a maximum junction temperature of less than 125°C. Therefore, Equation 19 can be used to calculate the number of devices (N) to be in parallel to support the maximum steady state DC load current (ILOAD(max)), for which the solution must be designed.

    Equation 19. N I O U T m a x   A 20   A

    According to Table 8-1, IOUT(max) is 80A. Therefore, 4 TPS1685 eFuses are connected in parallel.

  • Setting up the primary and secondary devices in a parallel configuration

    The MODE pin is used to configure one TPS1685x eFuse as the primary device in a parallel chain along with the other TPS1685x eFuses as the secondary devices. As a result, some of the TPS1685 pin functions can be changed to facilitate primary and secondary configuration as described in Multiple Devices, Parallel Connection.

    Leaving the pin open configures the corresponding device as the primary one. For the secondary devices, this pin must be connected to GND.

  • Selecting the CDVDT capacitor to control the output slew rate and start-up time

    A capacitor (CDVDT) must be added at the DVDT pin to GND to set the required value of slew rate. Equation 20 is used to compute the value of CDVDT. The DVDT pins of all the eFuses in a parallel chain must be connected together.

    Equation 20. C D V D T n F = 48 V I N V / T s s m s

    To get slew rate of 2.2V/ms , as per above equation we get CDVDT as 21.82nF. We can keep nearby standard value of 22nF.

  • Selecting the RIREF resistor to set the reference voltage for overcurrent protection and active current sharing

    In this parallel configuration, the IREF internal current source (IIREF) of the primary eFuse interacts with the external IREF pin resistor (RIREF) to generate the reference voltage (VIREF) for the overcurrent protection and active current sharing blocks. When the voltage at the IMON pin (VIMON) is used as an input to an ADC to monitor the system current or to implement the Platform Power Control (Intel PSYS) functionality inside the VR controller, VIREF must be set to half of the maximum voltage range of the ISYS_IN input of the controller. This action provides the necessary headroom and dynamic range for the system to accurately monitor the load current up to the fast-trip threshold (2 × IOCP). Equation 21 is used to calculate the value of RIREF.

    Equation 21. V I R E F = I I R E F × R I R E F

    In this design example, VIREF is set at 1V. With IIREF = 25µA (typical), we can calculate the target RIREF to be 40kΩ. The closest standard value of RIREF is 40.2kΩ with 0.1% tolerance and power rating of 100mW. For improved noise immunity, place a 100pF ceramic capacitor from the IREF pin to GND.

    Note:

    Maintain VIREF within the recommended voltage to ensure proper operation of overcurrent detection circuit.

  • Selecting the RIMON resistor to set the overcurrent (circuit-breaker) and fast-trip thresholds during steady-state

    TPS1685x eFuse responds to the output overcurrent conditions during steady-state by turning off the output after a user-adjustable transient fault blanking interval. This eFuse continuously senses the total system current (IOUT) and produces a proportional analog current output (IIMON) on the IMON pin. This generates a voltage (VIMON) across the IMON pin resistor (RIMON) in response to the load current, which is defined as Equation 22.

    Equation 22. V I M O N = I O U T × G I M O N × R I M O N

    GIMON is the current monitor gain (IIMON : IOUT), whose typical value is 18.2µA/A. The overcurrent condition is detected by comparing the VIMON against the VIREF as a threshold. The circuit-breaker threshold during steady-state (IOCP) can be calculated using Equation 23.

    Equation 23. I O C P ( T O T A L ) = V I R E F G I M O N × R I M O N

    In this design example, IOCP(TOTAL) is considered as 85A, and RIMON can be calculated to be 646.4Ω with GIMON as 18.2µA/A and VIREF as 1V. The nearest value of RIMON is 642Ω with 0.1% tolerance and power rating of 100mW. For noise reduction, place a 22pF ceramic capacitor across the IMON pin and GND.

    Note:

    System output current (IOUT) must be considered when selecting RIMON, not the current carried by each device.

  • Selecting the RILIM resistor to set active sharing threshold during steady-state

    RILIM is used in setting up the active current sharing threshold during steady-state. Each device continuously monitors the current flowing through it (IDEVICE) and outputs a proportional analog output current on its own ILIM pin. This in turn produces a proportional voltage (VILIM) across the respective ILIM pin resistor (RILIM), which is expressed as Equation 24.

    Equation 24. V I L I M = I D E V I C E × G I L I M × R I L I M

    GILIM is the current monitor gain (IILIM : IDEVICE), whose typical value is 20μA/A.

    • Active current sharing during steady-state: This mechanism operates only after the device reaches steady-state and acts independently by comparing its own load current information (VILIM) with the Active Current Sharing reference (CLREFLIN) threshold, defined as Equation 25.

      Equation 25. C L R E F L I N = 1.1 × V I R E F 3

      Therefore, RILIM must be calculated using Equation 26 to define the active current sharing threshold as IOCP(TOTAL)/N, where N is the number of devices in parallel. Using N = 4, RIMON = 642Ω, and Equation 26, RILIM can be calculated to be 235.4Ω. The closest standard value of 234Ω with 0.1% tolerance and power rating of 100mW resistances are selected as RILIM for each device.

      Equation 26. R I L I M = 1.1 × N × R I M O N 3
      Note:

      To determine the value of RILIM, Equation 27 must be used if a different threshold for active current sharing (ILIM(ACS)) than IOCP/N is desired.

      Equation 27. R I L I M = 1.1 × V I R E F 3 × G I L I M × I L I M ( A C S )
  • Selecting the CITIMER capacitor to set the overcurrent blanking timer

    An appropriate capacitor must be connected at the ITIMER pin to ground of the primary or standalone device to adjust the duration for which the load transients above the circuit-breaker threshold are allowed. The transient overcurrent blanking interval can be calculated using Equation 28.

    Equation 28. t I T I M E R m s = C I T I M E R n F × V I T I M E R V I I T I M E R μ A

    Where tITIMER is the transient overcurrent blanking timer and CITIMER is the capacitor connected between ITIMER pin of the primary device and GND. IITIMER = 2µA (typical) and ΔVITIMER = 1.3V (typical). A 4.7nF capacitor with 10% tolerance and DC voltage rating of 25V is used as the CITIMER for the primary device in this design, which results in 3ms of tITIMER. The ITIMER pin for all the secondary devices should be left open.

  • Selecting the resistors to set the undervoltage lockout threshold

    The undervoltage lockout (UVLO) threshold is adjusted by employing the external voltage divider network of R1 and R2 connected between IN, EN/UVLO, and GND pins of the device as described in Undervoltage protection section. The resistor values required for setting up the UVLO threshold are calculated using Equation 29.

    Equation 29. V I N U V = V U V L O R R 1 + R 2 R 2

    To minimize the input current drawn from the power supply, TI recommends using higher resistance values for R1 and R2. From the device electrical specifications, UVLO rising threshold VUVLO(R) = 1.2V. From the design requirements, VINUVLO = 46V. First choose the value of R1 = 3.74MΩ and use Equation 29 to calculate R2 = 100kΩ. Use the closest standard 1 % resistor values: R1 = 3.74MΩ and R2 = 100kΩ. For noise reduction, place a 100pF ceramic capacitor across the EN/UVLO pin and GND.

  • Selecting the resistors to set the overvoltage lockout threshold

    The overvoltage lockout (OVLO) threshold is adjusted by employing the external voltage divider network of R3 and R4 connected between IN, OVLO, and GND pins of the device as described in overvoltage protection section. The resistor values required for setting up the OVLO threshold are calculated using below equation.

    Equation 30. V I N O V = V O V L O R R 3 + R 4 R 4

    To minimize the input current drawn from the power supply, TI recommends using higher resistance values for R3 and R4. From the device electrical specifications, OVLO rising threshold VOVLO(R) = 1.164V. From the design requirements, VINOVLO = 60V. First choose the value of R1 = 5.11MΩ and use Equation 29 to calculate R3 = 101kΩ. Use the closest standard 1% resistor values: R3 = 5.11MΩ and R4 = 102kΩ. For noise reduction, place a 10pF ceramic capacitor across the OVLO pin and GND.

  • Selecting the R-C filter between VIN and VDD

    VDD pin is intended to power the internal control circuitry of the eFuse with a filtered and stable supply, not affected by system transients. Therefore, use an R (150Ω) – C (0.22µF) filter from the input supply (IN pin) to the VDD pin. This helps to filter out the supply noises and to hold up the controller supply during severe faults such as short-circuit at the output. In a parallel chain, this R-C filter must be employed for each device.

  • Selecting the pullup resistors and power supplies for PG, FLT,

    FLT, PG, are the open drain outputs. If these logic signals are used, the corresponding pins must be pulled up to an appropriate supply rail voltage through 33kΩ pullup resistances.

  • Selection of TVS diode at input and Schottky diode at output

    In the case of a short circuit and overload current limit when the device interrupts a large amount of current instantaneously, the input inductance generates a positive voltage spike on the input, whereas the output inductance creates a negative voltage spike on the output. The peak amplitudes of these voltage spikes (transients) are dependent on the value of inductance in series with the input or output of the device. Such transients can exceed the absolute maximum ratings of the device and eventually lead to failures due to electrical overstress (EOS) if appropriate steps are not taken to address this issue. Typical methods for addressing this issue include:

    1. Minimize lead length and inductance into and out of the device.
    2. Use a large PCB GND plane.
    3. Addition of the Transient Voltage Suppressor (TVS) diodes to clamp the positive transient spike at the input.
    4. Using Schottky diodes across the output to absorb negative spikes.

    Refer to TVS Clamping in Hot-Swap Circuits , Selecting TVS Diodes in Hot-Swap and ORing Applications, TVS Diode recommendation tool for details on selecting an appropriate TVS diode and the number of TVS diodes to be in parallel to effectively clamp the positive transients at the input below the absolute maximum ratings of the IN pin (20V). These TVS diodes also help to limit the transient voltage at the IN pin during the Hot Plug event. Four (4) SMDJ54A are used in parallel in this design example.

    Note:

    Maximum Clamping Voltage VC specification of the selected TVS diode at Ipp (10/1000μs) (V) must be lower than the absolute maximum rating of the power input (IN) pin for safe operation of the eFuse.

    Selection of the Schottky diodes must be based on the following criteria:

    • The non-repetitive peak forward surge current (IFSM) of the selected diode must be more than the fast-trip threshold (2 × IOCP(TOTAL)). Two or more Schottky diodes in parallel must be used if a single Schottky diode is unable to meet the required IFSM rating. Equation 31 calculates the number of Schottky diodes (NSchottky) that must be in parallel.
      Equation 31. N S c h o t t k y > 2 × I O C P T O T A L I F S M
    • Forward Voltage Drop (VF) at near to IFSM must be as small as possible. Ideally, the negative transient voltage at the OUT pin must be clamped within the absolute maximum rating of the OUT pin (–5V).
    • DC Blocking Voltage (VRM) must be more than the maximum input operating voltage.
    • Leakage current (IR) must be as small as possible.

    4 B360-13-F are used in parallel in this design example.

  • Selecting CIN and COUT

    TI recommends to add ceramic bypass capacitors to help stabilize the voltages on the input and output. The value of CIN must be kept small to minimize the current spike during hot-plug events. For each device, 0.01µF of CIN is a reasonable target. Because COUT does not get charged during hot-plug, a larger value such as 10µF can be used at the OUT pin of each device.