JAJSCP4 December   2016 TPS2065D

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: TJ = TA = 25°C
    6. 7.6 Electrical Characteristics: -40°C ≤ TJ ≤ 125°C
    7. 7.7 Timing Requirements: -40°C ≤ TJ ≤ 125°C
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout
      2. 8.3.2 Enable
      3. 8.3.3 Internal Charge Pump
      4. 8.3.4 Current Limit
      5. 8.3.5 FLT
      6. 8.3.6 Output Discharge
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input and Output Capacitance
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Power Dissipation and Junction Temperature
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

  1. Place the 100-nF bypass capacitor near the IN and GND pins, and make the connections using a low inductance trace.
  2. Place at least 10-µF low ESR ceramic capacitor near the OUT and GND pins, and make the connections using a low inductance trace.
  3. The PowerPAD™ should be directly connected to PCB ground plane using wide and short copper trace.

11.2 Layout Example

TPS2065D DBV_layout_lvsau6.gif Figure 32. DBV Package PCB Layout Example

11.3 Power Dissipation and Junction Temperature

It is good design practice to estimate power dissipation and maximum expected junction temperature of the TPS2065D. The system designer can control choices of package, proximity to other power dissipating devices, and printed-circuit-board (PCB) design based on these calculations. These have a direct influence on maximum junction temperature. Other factors, such as airflow and maximum ambient temperature, are often determined by system considerations. It is important to remember that these calculations do not include the effects of adjacent heat sources, and enhanced or restricted air flow.

Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and maintain the junction temperature as low as practical. The lower junction temperatures achieved by soldering the pad improve the efficiency and reliability of both device parts and the system. The following examples were used to determine the θJACustom thermal impedances noted in Thermal Information. They were based on use of the JEDEC high-k circuit board construction (2 signal and 2 plane) with 4, 1-oz. copper weight, layers.

As shown in Equation 1, the following procedure requires iteration because power loss is due to the internal MOSFET I2 × RDS(ON), and RDS(ON) is a function of the junction temperature. As an initial estimate, use the RDS(ON) at 125°C from the Typical Characteristics, and the preferred package thermal resistance for the preferred board construction from the Thermal Information table.

Equation 1. TJ = TA + ((IOUT2 × RDS(ON)) × θJA)

where

  • IOUT = rated OUT pin current (A)
  • RDS(ON) = Power switch on-resistance at an assumed TJ (Ω)
  • TA = Maximum ambient temperature (°C)
  • TJ = Maximum junction temperature (°C)
  • θJA = Thermal resistance (°C/W)

If the calculated TJ is substantially different from the original assumption, estimate a new value of RDS(ON) using the typical characteristic plot and recalculate.

If the resulting TJ is not less than 125°C, try a PCB construction and/or package with lower θJA.