8.3.1 Undervoltage Lockout

The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turnon threshold. Built-in hysteresis prevents unwanted ON/OFF cycling due to input voltage drop from large current surges. FLT is high impedance when the TPS2069D is in UVLO.

8.3.2 Enable

The logic enable input (EN), controls the power switch, bias for the charge pump, driver, and other circuits. The supply current is reduced to less than 1 µA when the TPS2069D is disabled. Disabling the TPS2069D immediately clears an active FLT indication. The enable input is compatible with both TTL and CMOS logic levels.

The turnon and turnoff times (t_ON, t_OFF) are composed of a delay and a rise or fall time (t_R, t_F). The delay times are internally controlled. The rise time is controlled by the device and the external loading (especially capacitance). TPS2069D fall time is controlled by the loading (R and C), and the output discharge (R_PD). An output load consisting of only a resistor will experience a fall time set by the device. An output load with parallel R and C elements experiences a fall time determined by the (R × C) time constant if it is longer than the device t_F.

The enable should not be left open, and may be tied to VIN or GND depending on the device.

8.3.3 Internal Charge Pump

The device incorporates an internal charge pump and gate drive circuitry necessary to drive the N-channel MOSFET. The charge pump supplies power to the gate driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The driver incorporates circuitry that controls the rise and fall times of the output voltage to limit large current and voltage surges on the input supply, and provides built-in soft-start functionality. The MOSFET power switch will block current from OUT to IN when turned off by the UVLO or disabled.

8.3.4 Current Limit

The TPS2069D responds to overloads by limiting output current to the static I_OS levels shown in Electrical Characteristics: TJ = TA = 25°C. When an overload condition is present, the device maintains a constant output current, with the output voltage determined by (I_OS × R_LOAD). Two possible overload conditions can occur.

The first overload condition occurs when either: 1) input voltage is first applied, enable is true, and a short circuit is present (load which draws I_OUT > I_OS), or 2) input voltage is present and the device is enabled into a short circuit. The output voltage is held near zero potential with respect to ground and the TPS2069D ramps the output current to I_OS. The device limits the current to I_OS until the overload condition is removed or the device begins to thermal cycle.

The second condition is when an overload occurs while the device is enabled and fully turned on. The device responds to the overload condition within t_IOS (Figure 5 and Figure 6) when the specified overload (see Electrical Characteristics: –40°C ≤ TJ ≤ 125°C) is applied. The response speed and shape varies with the overload level, input circuit, and rate of application. The current limit response will vary between simply settling to I_OS, or turnoff and controlled return to I_OS. Similar to the previous case, the device limits the current to I_OS until the overload condition is removed or the device begins to thermal cycle.

The TPS2069D thermal cycles if an overload condition is present long enough to activate thermal limiting in any of the above cases. This is due to the relatively large power dissipation [(V_IN – V_OUT) x I_OS] driving the junction temperature up. The device turns off when the junction temperature exceeds 135°C (minimum) while in current limit. The device remains off until the junction temperature cools 20°C and then restarts.

There are two kinds of current limit profiles typically available in TI switch products similar to the TPS2069D. Many older designs have an output I vs V characteristic similar to the plot labeled Current Limit with Peaking in Figure 21. This type of limiting can be characterized by two parameters, the current limit corner (I_OC), and the short circuit current (I_OS). I_OC is often specified as a maximum value. The TPS2069D does not present noticeable peaking in the current limit, corresponding to the characteristic labeled Flat Current Limit in Figure 21. This is why the I_OC parameter is not present in Electrical Characteristics: –40°C ≤ TJ ≤ 125°C.

Figure 21. Current Limit Profiles

8.3.5 FLT

The FLT open-drain output is asserted (active low) during an overload or overtemperature condition. A 9-ms deglitch on both the rising and falling edges avoids false reporting at start-up and during transients. A current limit condition shorter than the deglitch period clears the internal timer upon termination. The deglitch timer will not integrate multiple short overloads and declare a fault. This is also true for exiting from a faulted state. An input voltage with excessive ripple and large output capacitance may interfere with operation of FLT around I_OS as the ripple drives the device in and out of current limit.

If the TPS2069D is in current limit and the overtemperature circuit goes active, FLT goes true immediately; however, the exiting this condition is deglitched. FLT is tripped just as the knee of the constant-current limiting is entered. Disabling the device clears an active FLT as soon as the switch turns off. FLT is high impedance when the device is disabled or in undervoltage lockout (UVLO).

8.3.6 Output Discharge

A 470-Ω (typical) output discharge dissipates stored charge and leakage current on OUT when the TPS2069D is in UVLO or disabled. The pulldown circuit loses bias gradually as V_IN decreases, causing a rise in the discharge resistance as V_IN falls towards 0 V. The output is be controlled by an external loadings when the device is in ULVO or disabled.