JAJSOD0A April   2022  – July 2022 TPS22811

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
      1.      14
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO and UVP)
      2. 7.3.2 Overvoltage Lockout (OVLO)
      3. 7.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 7.3.3.1 Slew Rate (dVdt) and Inrush Current Control
        2. 7.3.3.2 Short-Circuit Protection
        3. 7.3.3.3 Active Current Limiting During Start-Up
      4. 7.3.4 Analog Load Current Monitor
      5. 7.3.5 Overtemperature Protection (OTP)
      6. 7.3.6 Fault Response
      7. 7.3.7 Power-Good Indication (PG)
      8. 7.3.8 Quick Output Discharge (QOD)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Single Device, Self-Controlled
      2. 8.1.2 Parallel Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting Undervoltage and Overvoltage Thresholds
        2. 8.2.2.2 Setting Output Voltage Rise Time (tR)
        3. 8.2.2.3 Setting Power-Good Assertion Threshold
        4. 8.2.2.4 Setting Analog Current Monitor Voltage (IMON) Range
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Transient Protection
    2. 9.2 Output Short-Circuit Measurements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.1 Layout Guidelines

  • For all applications, TI recommends a ceramic decoupling capacitor of 0.1 μF or greater between the IN terminal and GND terminal.

  • The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the GND terminal of the IC.

  • High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current.

  • The GND terminal must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection.

  • The IN and OUT pins are used for heat dissipation. Connect to as much copper area on top and bottom PCB layers using as possible with thermal vias. The vias under the device also help to minimize the voltage gradient across the IN and OUT pads and distribute current uniformly through the device, which is essential to achieve the best on-resistance and current sense accuracy.

  • Locate the following support components close to their connection pins:

    • RIMON

    • CdVdT

    • Resistors for the EN/UVLO, EN/OVLO pins

  • Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for the RIMON and CdVdt components to the device must be as short as possible to reduce parasitic effects on the current monitor and soft start timing. These traces must not have any coupling to switching signals on the board.

  • Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI also recommends to add a ceramic decoupling capacitor of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode/bypass-capacitor connection, the OUT pin and the GND terminal of the IC.