SLVSB49F November   2011  – January 2015 TPS22910A , TPS22912C

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Switching Characteristics, Typical
    7. 8.7  Typical DC Characteristics
    8. 8.8  Typical AC Characteristics, TPS22910A
    9. 8.9  Typical AC Characteristics, TPS22912C
    10. 8.10 Typical AC Characteristics, TPS22913B
    11. 8.11 Typical AC Characteristics, TPS22913C
  9. Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 On/Off Control
      2. 10.3.2 Under-Voltage Lockout
      3. 10.3.3 Full-Time Reverse Current Protection
    4. 10.4 Device Functional Modes
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 VIN to VOUT Voltage Drop
      2. 11.1.2 On/Off Control
      3. 11.1.3 Input Capacitor (Optional)
      4. 11.1.4 Output Capacitor (Optional)
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Inrush Current
      3. 11.2.3 Application Curves
        1. 11.2.3.1 Typical Application Characteristics for TPS22910A
        2. 11.2.3.2 Typical Application Characteristics for TPS22912C
        3. 11.2.3.3 Typical Application Characteristics For TPS22913B
        4. 11.2.3.4 Typical Application Characteristics for TPS22913C
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
    3. 13.3 Thermal Considerations
  14. 14Device and Documentation Support
    1. 14.1 Related Links
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
    4. 14.4 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

13 Layout

13.1 Layout Guidelines

For best performance, all traces should be as short as possible. To be most effective, the input and output capacitors should be placed close to the device to minimize the effects that parasitic trace inductances may have on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects along with minimizing the case to ambient thermal impedance.

13.2 Layout Example

The figure below shows an example for these devices. Notice the connection to system ground between the VOUT Bypass Capacitor ground and the GND pin of the load switch, this creates a ground barrier which helps to reduce the ground noise seen by the device.

layout_slvsci7.gif

13.3 Thermal Considerations

The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. To calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use the following equation as a guideline:

Equation 5. eq_thrm_slvsci4.gif

where

  • PD(max) = maximum allowable power dissipation
  • TJ(max) = maximum allowable junction temperature
  • TA = ambient temperature of the device
  • θJA = junction to air thermal impedance. See the Thermal Information section. This parameter is highly dependent upon board layout.