SLVS802C August   2009  – May  2015 TPS22932B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics, 1.2 V
    7. 7.7  Switching Characteristics, 1.5 V
    8. 7.8  Switching Characteristics, 1.8 V
    9. 7.9  Switching Characteristics, 2.5 V
    10. 7.10 Switching Characteristics, 3 V
    11. 7.11 Switching Characteristics, 3.3 V
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Configurable Logic Function
      2. 9.3.2 Quick Output Discharge
    4. 9.4 Device Functional Modes
      1. 9.4.1 Logic Configurations
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 ON and OFF Control
      2. 10.1.2 Input Capacitor
      3. 10.1.3 Output Capacitor
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 VIN to VOUT Voltage Drop
        2. 10.2.2.2 Managing Inrush Current
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Detailed Description

9.1 Overview

TPS22932B is a single-channel, low rON load switch with controlled turnon. The device contains a low rON P-channel MOSFET that can operate over an input voltage range of 1.1 V to 3.6 V. The switch is controlled by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All inputs can be connected to VIN or GND. The control pins can be connected to low-voltage GPIOs allowing it to be controlled by either 1.2-V, 1.8-V, 2.5-V, or 3.3-V logic signals while keeping extremely low quiescent current. A 120-Ω on-chip load resistor is available for output quick discharge when the switch is turned off. The rise time (slew rate) of the device is internally controlled to avoid inrush current.

9.2 Functional Block Diagram

TPS22932B abd_lvs802_v2.gif

9.3 Feature Description

9.3.1 Configurable Logic Function

The switch is controlled by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All inputs can be connected to VIN or GND. The control pins can be connected to low-voltage GPIOs allowing it to be controlled by either 1.2-V, 1.8-V, 2.5-V, or 3.3-V logic signals while keeping extremely low quiescent current.

9.3.2 Quick Output Discharge

The TPS22932B includes the Quick Output Discharge (QOD) feature. When the switch is disabled, a discharge resistance with a typical value of 120 Ω is connected between the output and ground. This resistance pulls down the output and prevents it from floating when the device is disabled.

9.4 Device Functional Modes

9.4.1 Logic Configurations

Table 1. Configurable Logic Function Table

INPUTS SWITCH CONTROL
ON3 ON2 ON1 Y
L L L OFF
L L H OFF
L H L ON
L H H ON
H L L OFF
H L H ON
H H L OFF
H H H ON
TPS22932B lbd_lvs802.gifFigure 31. Logic Diagram (Positive Logic)

Table 2. Function Selection Table

LOGIC FUNCTION FIGURE NO.
2-to-1 data selector Figure 32
2-input AND gate Figure 33
2-input OR gate with one inverted input Figure 34
2-input NAND gate with one inverted input Figure 34
2-input AND gate with one inverted input Figure 35
2-input NOR gate with one inverted input Figure 35
2-input OR gate Figure 36
Inverter Figure 37
Noninverted buffer Figure 38
TPS22932B logicconfig1_lvs802.gifFigure 32. 2-to-1 Data Selector
TPS22932B logicconfig2_lvs802.gifFigure 33. 2-Input AND Gate
TPS22932B logicconfig3_lvs802.gifFigure 34. 2-Input OR Gate With One Inverted Input, 2-Input NAND Gate With One Inverted Input
TPS22932B logicconfig4_lvs802.gifFigure 35. 2-Input AND Gate With One Inverted Input, 2-Input NOR Gate With One Inverted Input
TPS22932B logicconfig5_lvs802.gifFigure 36. 2-Input OR Gate
TPS22932B logicconfig6_lvs802.gifFigure 37. Inverter
TPS22932B logicconfig7_lvs802.gifFigure 38. Noninverted Buffer