JAJSN24A November   2021  – June 2022 TPS22953-Q1 , TPS22954-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3.     Recommended Operating Conditions
    4. 7.3  Thermal Information
    5. 7.4  Electrical Characteristics
    6. 7.5  Electrical Characteristics – VBIAS = 5 V
    7. 7.6  Electrical Characteristics – VBIAS = 3.3 V
    8. 7.7  Electrical Characteristics – VBIAS = 2.5 V
    9. 7.8  Switching Characteristics – CT = 1000 pF
    10. 7.9  Switching Characteristics – CT = 0 pF
    11. 7.10 Typical DC Characteristics
    12. 7.11 Typical Switching Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  On and Off Control (EN Pin)
      2. 9.3.2  Voltage Monitoring (SNS Pin)
      3. 9.3.3  Power Good (PG Pin)
      4. 9.3.4  Supervisor Fault Detection and Automatic Restart
      5. 9.3.5  Manual Restart
      6. 9.3.6  Thermal Shutdown
      7. 9.3.7  Reverse Current Blocking (TPS22953-Q1 Only)
      8. 9.3.8  Quick Output Discharge (QOD) (TPS22954-Q1 Only)
      9. 9.3.9  VIN and VBIAS Voltage Range
      10. 9.3.10 Adjustable Rise Time (CT Pin)
      11. 9.3.11 Power Sequencing
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input to Output Voltage Drop
      2. 10.1.2 Thermal Considerations
      3. 10.1.3 Automatic Power Sequencing
      4. 10.1.4 Monitoring a Downstream Voltage
      5. 10.1.5 Monitoring the Input Voltage
      6. 10.1.6 Break-Before-Make Power MUX (TPS22953-Q1 Only)
      7. 10.1.7 Make-Before-Break Power MUX (TPS22953-Q1 Only)
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inrush Current
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.10 Adjustable Rise Time (CT Pin)

A capacitor to GND on the CT pin sets the slew rate for VOUT. An appropriate capacitance value must be placed on CT such that the IMAX and IPLS specifications of the device are not violated. The capacitor to GND on the CT pin must be rated for 25 V or higher. Equation 4 shows an approximate formula for the relationship between CT (except for CT = open) and the slew rate for any VBIAS.

Equation 4. SR = 0.35 × CT + 20

where

  • SR is the slew rate (in μs/V).
  • CT is the capacitance value on the CT terminal (in pF).
  • The units for the constant 20 are μs/V.
  • The units for the constant 0.35 are μs/(V*pF).

Rise time can be calculated by multiplying the input voltage (typically 10% to 90%) by the slew rate. Table 9-1 contains rise time values measured on a typical device.

Table 9-1 Rise Time
CTx (pF)RISE TIME (µs) 10% – 90%, CL = 0.1 µF, VBIAS = 2.5 V to 5.7 V, RL = 10-Ω LOAD.
TYPICAL VALUES AT 25°C, 25-V X7R 10% CERAMIC CAP
5 V3.3 V1.8 V1.5 V1.2 V0.7 V
Open1409862544632
22044430117515012481
470767518299255210133
10001492994562474387245
2200310520501151961787490
470064204246236519801612998
100001405993395183433135332197