JAJSN24A November   2021  – June 2022 TPS22953-Q1 , TPS22954-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3.     Recommended Operating Conditions
    4. 7.3  Thermal Information
    5. 7.4  Electrical Characteristics
    6. 7.5  Electrical Characteristics – VBIAS = 5 V
    7. 7.6  Electrical Characteristics – VBIAS = 3.3 V
    8. 7.7  Electrical Characteristics – VBIAS = 2.5 V
    9. 7.8  Switching Characteristics – CT = 1000 pF
    10. 7.9  Switching Characteristics – CT = 0 pF
    11. 7.10 Typical DC Characteristics
    12. 7.11 Typical Switching Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  On and Off Control (EN Pin)
      2. 9.3.2  Voltage Monitoring (SNS Pin)
      3. 9.3.3  Power Good (PG Pin)
      4. 9.3.4  Supervisor Fault Detection and Automatic Restart
      5. 9.3.5  Manual Restart
      6. 9.3.6  Thermal Shutdown
      7. 9.3.7  Reverse Current Blocking (TPS22953-Q1 Only)
      8. 9.3.8  Quick Output Discharge (QOD) (TPS22954-Q1 Only)
      9. 9.3.9  VIN and VBIAS Voltage Range
      10. 9.3.10 Adjustable Rise Time (CT Pin)
      11. 9.3.11 Power Sequencing
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input to Output Voltage Drop
      2. 10.1.2 Thermal Considerations
      3. 10.1.3 Automatic Power Sequencing
      4. 10.1.4 Monitoring a Downstream Voltage
      5. 10.1.5 Monitoring the Input Voltage
      6. 10.1.6 Break-Before-Make Power MUX (TPS22953-Q1 Only)
      7. 10.1.7 Make-Before-Break Power MUX (TPS22953-Q1 Only)
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inrush Current
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.2 Voltage Monitoring (SNS Pin)

The SNS pin of the device can be used to monitor the output voltage of the device or another voltage rail. The pin can be configured with an external resistor divider to set the desired trip point for the voltage being monitored or be tied to OUT directly. If the voltage on the SNS pin exceeds VIH,SNS, the voltage being monitored on the SNS pin is considered to be valid high. The voltage on the SNS pin must be greater than VIH,SNS for at least tBLANK before PG is asserted high. If the voltage on the SNS pin goes below VIL,SNS, then the switch powers cycle (that is, the switch is disabled and re-enabled). For proper functionality of the device, this pin must not be left floating. If a resistor divider is not being used for voltage sensing, this pin can be tied directly to VOUT.

The SNS pin has a blanking time of tBLANK on the rising edge after the VIH,SNS threshold has been exceeded. The SNS pin has a de-glitch time of tDEGLITCH when the voltage has gone below VIL,SNS.

See Equation 2 and Figure 9-2 on how to configure the SNS pin for voltage monitoring.

Equation 2. GUID-3E368565-114B-48EA-8BDA-8FE9C2B7040F-low.gif

where

  • VIH,SNS is the the rising threshold of the SNS pin (see Electrical Characteristics table)
  • VOUT is the voltage on the OUTpin
  • RSNS1, RSNS2 are the resistor divider values
GUID-1E33DA95-32A5-4F9D-B103-7B030B6CAE8F-low.gifFigure 9-2 Voltage Divdier (SNS Pin)