SLVSCI4B February 2014 – September 2014 TPS22961
PRODUCTION DATA.
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NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
This section will highlight some of the design considerations when implementing this device in various applications. A PSPICE model for this device is also available in the product page of this device on www.ti.com for further aid.
This application demonstrates how the TPS22961 can be used to power downstream modules.
For this design example, use the following as the input parameters.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
VIN | 1.05 V |
VBIAS | 5.0 V |
Load current | 6 A |
To begin the design process, the designer needs to know the following:
The VIN to VOUT voltage drop in the device is determined by the RON of the device and the load current. The RON of the device depends upon the VIN and VBIAS conditions of the device. Refer to the RON specification of the device in the Electrical Characteristics table of this datasheet. Once the RON of the device is determined based upon the VIN and VBIAS conditions, use Equation 1 to calculate the VIN to VOUT voltage drop:
where
An appropriate ILOAD must be chosen such that the IMAX specification of the device is not violated.
To determine how much inrush current will be caused by the CL capacitor, use Equation 2:
where
An appropriate CL value should be placed on VOUT such that the IMAX and IPLS specficiations of the device are not violated.
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. To calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use Equation 3.
where
VBIAS = 5 V | VIN = 2.5 V | CIN = 1 µF |
CL = 0.1 µF |
VBIAS = 5 V | VIN = 1.05 V | CIN = 1 µF |
CL = 0.1 µF |
VBIAS = 5 V | VIN = 0.8 V | CIN = 1 µF |
CL = 0.1 µF |
VBIAS = 5 V | VIN = 0.8 V | CIN = 1 µF |
CL = 0.1 µF |
This application demonstrates how the TPS22961 can be used to power rails senstive to ringing and overvoltage that can often happen due to fast rise times.
For this design example, use the following as the input parameters.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
VIN | 1.05 V |
VBIAS | 5.0 V |
Acceptable percent overshoot (ρ) | 3.2% |
Maximum settling time (tSETTLE) | 40 µs |
To begin the design process, the designer needs to know the following:
To determine the value of L and CL in the circuit, the damping factor associated with the acceptable percent overshoot must be calculated. To calculate the damping factor (ε), use Equation 4.
where
Use the damping factor calculated in Equation 4 to determine the inductance (L), the DCR of the inductor (RDCR), and capacitance (CL) to achieve the percent overshoot. This will be an iterative process to determine the optimal combination of L and CL with standard value components available. Use Equation 5 to determine the combination of L, RDCR, and CL that is needed to satisfy damping factor calculated from Equation 4.
where
To determine the setting time (within 5% of steady state value) of the filter, use Equation 6.
where
The combination of damping factor (ε) and filter settling time (tSETTLE) will bound the values for L, RDCR, and CL that can be used to meet the design constraints in Table 2.