JAJSIF0E
April 2014 – July 2022
TPS22965-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics—VBIAS = 5 V
7.6
Electrical Characteristics—VBIAS = 2.5 V
7.7
Switching Characteristics
7.8
Typical Characteristics
7.8.1
Typical DC Characteristics
7.8.2
Typical Switching Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Adjustable Rise Time
9.3.2
Quick Output Discharge (TPS22965-Q1 and TPS22965W-Q1 Only)
9.3.3
Low Power Consumption During OFF State
9.4
Device Functional Modes
10
Application and Implementation
10.1
Application Information
10.1.1
VIN to VOUT Voltage Drop
10.1.2
On and Off Control
10.1.3
Input Capacitor (Optional)
10.1.4
Output Capacitor (Optional)
10.1.5
VIN and VBIAS Voltage Range
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Inrush Current
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
12.3
Thermal Consideration
13
Device and Documentation Support
13.1
Documentation Support
13.1.1
Related Documentation
13.2
Receiving Notification of Documentation Updates
13.3
サポート・リソース
13.4
Trademarks
13.5
Electrostatic Discharge Caution
13.6
Glossary
14
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DSG|8
MPDS308C
サーマルパッド・メカニカル・データ
DSG|8
QFND569C
発注情報
jajsif0e_oa
jajsif0e_pm
12.2
Layout Example
A.
Thermal relief vias. Thermal relief vias connected to the exposed thermal pad.
Figure 12-1
Layout Recommendation