JAJSIF0E April   2014  – July 2022 TPS22965-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics—VBIAS = 5 V
    6. 7.6 Electrical Characteristics—VBIAS = 2.5 V
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
      1. 7.8.1 Typical DC Characteristics
      2. 7.8.2 Typical Switching Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Adjustable Rise Time
      2. 9.3.2 Quick Output Discharge (TPS22965-Q1 and TPS22965W-Q1 Only)
      3. 9.3.3 Low Power Consumption During OFF State
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 VIN to VOUT Voltage Drop
      2. 10.1.2 On and Off Control
      3. 10.1.3 Input Capacitor (Optional)
      4. 10.1.4 Output Capacitor (Optional)
      5. 10.1.5 VIN and VBIAS Voltage Range
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inrush Current
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Consideration
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.1 Adjustable Rise Time

A capacitor to GND on the CT pin sets the slew rate. The voltage on the CT pin can be as high as 12 V. Therefore, the minimum voltage rating for the CT cap must be 25 V for optimal performance. The below equations shows an approximate formula for the relationship between CT and slew rate when VBIAS is set to 5 V. This equation accounts for 10% to 90% measurement on VOUT and does not apply for CT = 0 pF. Use the below equation to determine rise times for when CT = 0 pF.

Equation 1. GUID-13282B5C-2A34-4208-AF44-29460B393A2D-low.gif

where

  • SR = slew rate (in µs/V).
  • CT = the capacitance value on the CT pin (in pF).
  • The units for the constant 34 are µs/V. The units for the constant 0.38 are µs/(V × pF).

Rise time can be calculated by multiplying the input voltage by the slew rate. Table 9-1 contains rise time values measured on a typical device. The rise times listed in Table 9-1 are only valid for the power-up sequence where VIN and VBIAS are already in steady state condition before the ON pin is asserted high.

Table 9-1 Rise Time vs CT Capacitor
CT (pF)RISE TIME (µs) 10% - 90%, CL = 0.1 µF, CIN = 1 µF, RL = 10 Ω, VBIAS = 5 V (1)
VIN = 5 VVIN = 3.3 VVIN = 1.8 VVIN = 1.5 VVIN = 1.2 VVIN = 1.05 VVIN = 0.8 V
01801369484747060
220547378232202173157129
470962654386333282252206
100019831330765647533476382
220040132693153713101077959766
47008207549031372693220019701590
10000177001176766975683465741513350
(1) Typical Values at 25°C with a 25-V X7R 10% Ceramic Capacitor on CT