JAJSIO1B December   2013  – March 2020 TPS22966-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VBIAS = 5 V
    6. 6.6 Electrical Characteristics: VBIAS = 2.5 V
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
      1. 6.8.1 Typical AC Scope Captures at TA = 25ºC, CT = 1 nF
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Quick Output Discharge
      2. 8.3.2 ON/OFF Control
      3. 8.3.3 Adjustable Rise Time
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Capacitor (Optional)
      2. 9.1.2 Output Capacitor (Optional)
      3. 9.1.3 VIN and VBIAS Voltage Range
      4. 9.1.4 Safe Operating Area (SOA)
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 商標
    2. 12.2 静電気放電に関する注意事項
    3. 12.3 Glossary
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 サポート・リソース
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DPU Package
14-Pin WSON
TPS22966-Q1 pinout_lvsbh4.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 VIN1 I Switch 1 input. Place an optional decoupling capacitor between this pin and GND for reduce VIN dip during turnon of the channel. See Application Information section for more information.
2 VIN1 I Switch 1 input. Place an optional decoupling capacitor between this pin and GND for reduce VIN dip during turnon of the channel. See Application Informationfor more information.
3 ON1 I Active high switch 1 control input. Do not leave floating.
4 VBIAS I Bias voltage. Power supply to the device. See Application Information for more information.
5 ON2 I Active high switch 2 control input. Do not leave floating.
6 VIN2 I Switch 2 input. Place an optional decoupling capacitor between this pin and GND for reduce VIN dip during turnon of the channel. See Application Information for more information.
7 VIN2 I Switch 2 input. Place an optional decoupling capacitor between this pin and GND for reduce VIN dip during turnon of the channel. See Application Information for more information.
8 VOUT2 O Switch 2 output.
9 VOUT2 O Switch 2 output.
10 CT2 O Switch 2 slew rate control. Can be left floating. Capacitor used on this pin should be rated for a minimum of 25 V for desired rise time performance.
11 GND – Ground
12 CT1 O Switch 1 slew rate control. Can be left floating. Capacitor used on this pin should be rated for a minimum of 25 V for desired rise time performance.
13 VOUT1 O Switch 1 output.
14 VOUT1 O Switch 1 output.
15 Thermal Pad O Thermal pad (exposed center pad) to alleviate thermal stress. Tie to GND. See Layout Guidelines for layout guidelines.