JAJSES8B October   2017  – November 2018 TPS2372

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PG Power Good (Converter Enable) Pin Interface
      2. 7.3.2 CLSA and CLSB Classification, AUTCLS
      3. 7.3.3 DEN Detection and Enable
      4. 7.3.4 Internal Pass MOSFET and Inrush Delay Enable, IRSHDL_EN
      5. 7.3.5 TPH, TPL and BT PSE Type Indicators
      6. 7.3.6 AMPS_CTL, MPS_DUTY and Automatic MPS
      7. 7.3.7 VDD Supply Voltage
      8. 7.3.8 VSS
      9. 7.3.9 Exposed Thermal PAD
    4. 7.4 Device Functional Modes
      1. 7.4.1  PoE Overview
      2. 7.4.2  Threshold Voltages
      3. 7.4.3  PoE Startup Sequence
      4. 7.4.4  Detection
      5. 7.4.5  Hardware Classification
      6. 7.4.6  Autoclass
      7. 7.4.7  Inrush and Startup
      8. 7.4.8  Maintain Power Signature
      9. 7.4.9  Startup and Converter Operation
      10. 7.4.10 PD Hotswap Operation
      11. 7.4.11 Startup and Power Management, PG and TPH, TPL, BT
      12. 7.4.12 Using DEN to Disable PoE
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Requirements
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistors, RCLSA and RCLSB
        6. 8.2.2.6  Opto-isolators for TPH, TPL and BT
        7. 8.2.2.7  Automatic MPS and MPS Duty Cycle, RMPS and RMPS_DUTY
        8. 8.2.2.8  Internal Voltage Reference, RREF
        9. 8.2.2.9  Autoclass
        10. 8.2.2.10 Inrush Delay
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 EMI Containment
    4. 10.4 Thermal Considerations and OTSD
    5. 10.5 ESD
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連リンク
      2. 11.1.2 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGW|20
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Unless otherwise noted, 40 V ≤ VVDD ≤ 57 V; RDEN = 24.9 kΩ; PG, CLSA, CLSB, MPS_DUTY, AMPS_CTL, IRSHDL_EN, TPH, TPL and BT open; VAUTCLS = VVSS; RREF = 49.9 kΩ; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to VVSS unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DETECTION (DEN)
Bias current DEN open, VVDD = 10.1 V, Measure ISUPPLY(VDD, RTN, DEN), Not in mark 3 4.8 14 µA
DEN leakage current VDEN = VVDD = 57 V 0.5 5 µA
Detection current Measure ISUPPLY(VDD, RTN, DEN), VVDD = 1.4 V 53.8 56.5 58.3 µA
Measure ISUPPLY(VDD, RTN, DEN), VVDD = 10.1 V, Not in mark 395 410 417
VPD_DIS Disable threshold DEN falling 3 3.7 5 V
Hysteresis 75 150 250 mV
CLASSIFICATION (CLS)
ICLS Classification A,B signature current 13 V ≤ VVDD ≤ 21 V, Measure IVDD + IDEN + IRTN
RCLSA or RCLSB = 1210 Ω 2.1 2.5 2.9 mA
RCLSA or RCLSB = 249 Ω 9.9 10.6 11.2
RCLSA or RCLSB = 140 Ω 17.6 18.6 19.4
RCLSA or RCLSB = 90.9 Ω 26.5 27.9 29.3
RCLSA or RCLSB = 63.4 Ω 38 39.9 42
IAUTCLS Autoclass signature current After tACS during 1st Class event 1 4 mA
VCL_ON Class lower threshold VVDD rising, ICLS ↑ 11.9 12.5 13 V
VCL_H Hysteresis 1.4 1.6 1.7
VCU_ON Class upper threshold VVDD rising, ICLS↓ 21 22 23 V
VCU_H Hysteresis 0.5 0.78 0.9
VMSR Mark reset threshold VVDD falling 3 3.9 5 V
Mark state resistance 2-point measurement at 5 V and 10.1 V 6 10 12 kΩ
Leakage current VVDD = 57 V, VCLS = 0 V, measure ICLS 1 µA
tLCF_PD Long first class event timing Class 1st event time duration for new MPS 76 81.5 86 ms
tACS Autoclass signature timing AUTCLS During Class 1st event 76 81.5 87 ms
AUTCLS pullup current 13 V ≤ VVDD ≤ 21 V 30 34 38 μA
PASS DEVICE (RTN)
rDS(on) On resistance TPS2372-3 0.3 0.55 Ω
TPS2372-4 0.1 0.2
Input bias current VVDD = VRTN = 30 V, measure IRTN 50 µA
RTN leakage current VVDD = VRTN = 100 V, VDEN = VVSS , measure IRTN 80
Current limit VRTN = 1.5 V TPS2372-3 1.55 1.85 2.2 A
VRTN = 1.5 V TPS2372-4 1.9 2.2 2.5
Inrush current limit VRTN = 2 V,
VVDD: 20 V → 48 V		 TPS2372-3 165 200 237 mA
VRTN = 2 V,
VVDD: 20 V → 48 V		 TPS2372-4 275 335 395
Inrush termination Percentage of inrush current 65% 90% 99%
tINR_DEL Inrush delay 78 81.5 87 ms
Foldback threshold VRTN rising 12.5 14.5 15.5 V
Foldback deglitch time VRTN rising to when current limit changes to inrush current limit 1.35 1.65 1.95 ms
POWER GOOD (PG)
Output low voltage Measure VPG – VRTN, IPG = 2 mA, VRTN = 2 V, VDD: 20 V → 48 V 0.27 0.5 V
Leakage current VPG = 57 V, VRTN = 0 V 10 μA
VPG = 10 V, VRTN = 0 V 1
PSE TYPE INDICATION (TPL, TPH,BT)
VTPL Output low voltage ITPL = 2 mA, after 2-, 3- or 5-event classification, startup has completed,
VRTN = 0 V		 0.27 0.5 V
VTPH Output low voltage ITPH = 2 mA, after 4- or 5-event classification, startup has completed, VRTN = 0 V 0.27 0.5
VBT Output low voltage IBT = 2 mA, after IEEE802.3bt classification, startup has completed, VRTN = 0 V 0.27 0.5
Leakage current VTPL or VTPH or VBT = 7 V, VRTN = 0 V 1 µA
tTPLHBT TPL, TPH, BT delay From PG: Low → open during startup to TPH and/or TPL and/or BT active 20 24 28 ms
UVLO
VUVLO_R UVLO rising threshold VVDD rising 36.3 38.1 40 V
VUVLO_F UVLO falling threshold VVDD falling 30.5 32 33.6
VUVLO_H UVLO hysteresis 6.1 V
BIAS CURRENT
Operating current 40 V ≤ VVDD ≤ 57 V, startup has completed 550 800 µA
MPS
MPS DC supply current Startup has completed, IRTN = 0 mA 0.8 mA
AMPS_CTL pulsed voltage Startup has completed, IRTN < 20 mA,
RMPS = 1 KΩ to 12 kΩ		 23.1 24 24.9 V
Automatic MPS falling current threshold Startup has completed, IRTN threshold to generate AMPS_CTL pulses 18 28 38 mA
Hysteresis on RTN current 1
MPS pulsed mode duty cycle for Type 1-2 PSE MPS pulsed current duty cycle 25.8% 26.1% 26.4%
MPS pulsed current ON time 76 81.5 87 ms
MPS pulsed current OFF time 230 250
MPS pulsed mode duty cycle for Type 3-4 PSE MPS pulsed current duty cycle,
RMPS_DUTY > 230 kΩ		 5.2% 5.43% 5.6%
MPS pulsed current ON time,
RMPS_DUTY > 230 kΩ		 14.5 15.0 15.7 ms
MPS pulsed current duty cycle,
RMPS_DUTY < 8 kΩ		 12.3% 12.5% 12.7%
MPS pulsed current ON time,
RMPS_DUTY < 8 kΩ		 36 37.5 39 ms
MPS pulsed current duty cycle,
43 kΩ < RMPS_DUTY < 77 kΩ		 7.9% 8.1% 8.3%
MPS pulsed current ON time,
43 kΩ < RMPS_DUTY < 77 kΩ		 22.2 23.1 24 ms
MPS pulsed current OFF time, RMPS_DUTY from 0 Ω to open circuit 250 263.5 277 ms
MPS_DUTY pullup current 14 17 20 µA
THERMAL SHUTDOWN
Shutdown TJ↑ 140 158 °C
Hysteresis (1) 20 °C
(1) Parameters provided for reference only, and do not constitute part of TI published specifications for purposes of TI product warranty.