JAJSES8B October   2017  – November 2018 TPS2372

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PG Power Good (Converter Enable) Pin Interface
      2. 7.3.2 CLSA and CLSB Classification, AUTCLS
      3. 7.3.3 DEN Detection and Enable
      4. 7.3.4 Internal Pass MOSFET and Inrush Delay Enable, IRSHDL_EN
      5. 7.3.5 TPH, TPL and BT PSE Type Indicators
      6. 7.3.6 AMPS_CTL, MPS_DUTY and Automatic MPS
      7. 7.3.7 VDD Supply Voltage
      8. 7.3.8 VSS
      9. 7.3.9 Exposed Thermal PAD
    4. 7.4 Device Functional Modes
      1. 7.4.1  PoE Overview
      2. 7.4.2  Threshold Voltages
      3. 7.4.3  PoE Startup Sequence
      4. 7.4.4  Detection
      5. 7.4.5  Hardware Classification
      6. 7.4.6  Autoclass
      7. 7.4.7  Inrush and Startup
      8. 7.4.8  Maintain Power Signature
      9. 7.4.9  Startup and Converter Operation
      10. 7.4.10 PD Hotswap Operation
      11. 7.4.11 Startup and Power Management, PG and TPH, TPL, BT
      12. 7.4.12 Using DEN to Disable PoE
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Requirements
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistors, RCLSA and RCLSB
        6. 8.2.2.6  Opto-isolators for TPH, TPL and BT
        7. 8.2.2.7  Automatic MPS and MPS Duty Cycle, RMPS and RMPS_DUTY
        8. 8.2.2.8  Internal Voltage Reference, RREF
        9. 8.2.2.9  Autoclass
        10. 8.2.2.10 Inrush Delay
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 EMI Containment
    4. 10.4 Thermal Considerations and OTSD
    5. 10.5 ESD
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連リンク
      2. 11.1.2 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGW|20
サーマルパッド・メカニカル・データ
発注情報

10.3 EMI Containment

  • Use compact loops for dv/dt and di/dt circuit paths (power loops and gate drives).
  • Use minimal, yet thermally adequate, copper areas for heat sinking of components tied to switching nodes (minimize exposed radiating surface).
  • Use copper ground planes (possible stitching) and top layer copper floods (surround circuitry with ground floods).
  • Use 4 layer PCB if economically feasible (for better grounding).
  • Minimize the amount of copper area associated with input traces (to minimize radiated pickup).
  • Use Bob Smith terminations, Bob Smith EFT capacitor, and Bob Smith plane.
  • Use Bob Smith plane as ground shield on input side of PCB (creating a phantom or literal earth ground).
  • Use of ferrite beads on input (allow for possible use of beads or 0-Ω resistors).
  • Maintain physical separation between input-related circuitry and power circuitry (use ferrite beads as boundary line).
  • Possible use of common-mode inductors.
  • Possible use of integrated RJ-45 jacks (shielded with internal transformer and Bob Smith terminations).
  • End-product enclosure considerations (shielding).