JAJSDX9C June   2017  – November 2018 TPS2373

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  APD Auxiliary Power Detect
      2. 7.3.2  PG Power Good (Converter Enable) Pin Interface
      3. 7.3.3  CLSA and CLSB Classification
      4. 7.3.4  DEN Detection and Enable
      5. 7.3.5  Internal Pass MOSFET
      6. 7.3.6  TPH, TPL and BT PSE Type Indicators
      7. 7.3.7  VC_IN, VC_OUT, UVLO_SEL, and Advanced PWM Startup
      8. 7.3.8  AMPS_CTL, MPS_DUTY and Automatic MPS
      9. 7.3.9  VDD Supply Voltage
      10. 7.3.10 VSS
      11. 7.3.11 Exposed Thermal PAD
    4. 7.4 Device Functional Modes
      1. 7.4.1  PoE Overview
      2. 7.4.2  Threshold Voltages
      3. 7.4.3  PoE Startup Sequence
      4. 7.4.4  Detection
      5. 7.4.5  Hardware Classification
      6. 7.4.6  Inrush and Startup
      7. 7.4.7  Maintain Power Signature
      8. 7.4.8  Advanced Startup and Converter Operation
      9. 7.4.9  PD Hotswap Operation
      10. 7.4.10 Startup and Power Management, PG and TPH, TPL, BT
      11. 7.4.11 Adapter ORing
      12. 7.4.12 Using DEN to Disable PoE
      13. 7.4.13 ORing Challenges
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Requirements
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistors, RCLSA and RCLSB
        6. 8.2.2.6  APD Pin Divider Network RAPD1, RAPD2
        7. 8.2.2.7  Opto-isolators for TPH, TPL and BT
        8. 8.2.2.8  VC Input and Output, CVCIN and CVCOUT
        9. 8.2.2.9  UVLO Select, UVLO_SEL
        10. 8.2.2.10 Automatic MPS and MPS Duty Cycle, RMPS and RMPS_DUTY
        11. 8.2.2.11 Internal Voltage Reference, RREF
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 EMI Containment
    4. 10.4 Thermal Considerations and OTSD
    5. 10.5 ESD
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGW|20
サーマルパッド・メカニカル・データ
発注情報

7.3.6 TPH, TPL and BT PSE Type Indicators

The state of BT, TPH and TPL is used to provide information relative to the PSE Type (1-2 or 3-4) and its allocated power. Table 2 lists the encoding corresponding to various combinations of PSE Type, PD Class and allocated power. Table 3 also corresponds to cases where the PSE allocated power is lower than what the PD is requesting. The allocated power is determined by the number of classification cycles having been received. During startup, the TPH, TPL and BT outputs are enabled typically 24 ms after VVC_IN went high, to allow the power supply to reach a stable state first. In applications where VC_IN is tied to a DC voltage already present before end of inrush, the 24-ms delay applies from when PG output went from low to open state. These 3 outputs will return to a high-impedance state if the part enters thermal shutdown, if VC_OUT voltage falls below its UVLO threshold, or if VDD-to-VSS voltage falls below ~32 V. Note that in all these cases, as long as VDD-to-VSS voltage remains above the mark reset threshold, the internal logic state of these 3 signals is remembered such that these outputs will be activated accordingly after the startup has completed. This circuit resets when the VDD-to-VSS voltage drops below the mark reset threshold. The TPH, TPL and BT pins can be left unconnected if not used.

Table 2. TPH, TPL, BT and Allocated Power Truth Table

PSE Type PD Class NUMBER OF CLASS CYCLES PSE ALLOCATED POWER AT PD (W) TPH TPL BT(1)
1-2 0 1 12.95 HIGH HIGH HIGH
1-2 1 1 3.84 HIGH HIGH HIGH
1-2 2 1 6.49 HIGH HIGH HIGH
1-2 3 1 12.95 HIGH HIGH HIGH
2 4 2 25.5 HIGH LOW HIGH
3-4 0 1 12.95 HIGH HIGH LOW
3-4 1 1 3.84 HIGH HIGH LOW
3-4 2 1 6.49 HIGH HIGH LOW
3-4 3 1 12.95 HIGH HIGH LOW
3-4 4 2-3 25.5 HIGH LOW LOW
3-4 5 4 40 LOW HIGH LOW
3-4 6 4 51 LOW HIGH LOW
4 7 5 62 LOW LOW LOW
4 8 5 71 LOW LOW LOW
(1) The BT output is not required to indicate how much power is allocated to the PD by a IEEE802.3bt compliant PSE. Additional information may be provided depending on the application described in the Application Detailed Design Requirements section Opto-isolators for TPH, TPL and BT

Table 3. Power Demotion Cases

PSE Type PD Class NUMBER OF CLASS CYCLES PSE ALLOCATED POWER AT PD (W) TPH TPL BT
3-4 4-8 1 12.95 HIGH HIGH LOW
3-4 5-8 2,3 25.5 HIGH LOW LOW
3-4 7-8 4 51 LOW HIGH LOW