JAJSDX9C June   2017  – November 2018 TPS2373

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  APD Auxiliary Power Detect
      2. 7.3.2  PG Power Good (Converter Enable) Pin Interface
      3. 7.3.3  CLSA and CLSB Classification
      4. 7.3.4  DEN Detection and Enable
      5. 7.3.5  Internal Pass MOSFET
      6. 7.3.6  TPH, TPL and BT PSE Type Indicators
      7. 7.3.7  VC_IN, VC_OUT, UVLO_SEL, and Advanced PWM Startup
      8. 7.3.8  AMPS_CTL, MPS_DUTY and Automatic MPS
      9. 7.3.9  VDD Supply Voltage
      10. 7.3.10 VSS
      11. 7.3.11 Exposed Thermal PAD
    4. 7.4 Device Functional Modes
      1. 7.4.1  PoE Overview
      2. 7.4.2  Threshold Voltages
      3. 7.4.3  PoE Startup Sequence
      4. 7.4.4  Detection
      5. 7.4.5  Hardware Classification
      6. 7.4.6  Inrush and Startup
      7. 7.4.7  Maintain Power Signature
      8. 7.4.8  Advanced Startup and Converter Operation
      9. 7.4.9  PD Hotswap Operation
      10. 7.4.10 Startup and Power Management, PG and TPH, TPL, BT
      11. 7.4.11 Adapter ORing
      12. 7.4.12 Using DEN to Disable PoE
      13. 7.4.13 ORing Challenges
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Requirements
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistors, RCLSA and RCLSB
        6. 8.2.2.6  APD Pin Divider Network RAPD1, RAPD2
        7. 8.2.2.7  Opto-isolators for TPH, TPL and BT
        8. 8.2.2.8  VC Input and Output, CVCIN and CVCOUT
        9. 8.2.2.9  UVLO Select, UVLO_SEL
        10. 8.2.2.10 Automatic MPS and MPS Duty Cycle, RMPS and RMPS_DUTY
        11. 8.2.2.11 Internal Voltage Reference, RREF
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 EMI Containment
    4. 10.4 Thermal Considerations and OTSD
    5. 10.5 ESD
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGW|20
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RGW Package
20-Pin VQFN
Top View
TPS2373 PINOUT_SLUSCD1.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
VDD 1 I Connect to positive PoE input power rail. Bypass with 0.1 µF to VSS.
DEN 2 I/O Connect a 24.9 kΩ resistor from DEN to VDD to provide the PoE detection signature. Pull DEN to VSS to disable the pass MOSFET during powered operation.
CLSA 3 O Connect a resistor from CLSA to VSS to program the first classification current.
VSS 4, 5 — Connect to negative power rail derived from PoE source.
CLSB 6 O Connect a resistor from CLSB to VSS to program the second classification current.
REF 7 O Internal 1.5 V voltage reference. Connect a 49.9kΩ_1% resistor from REF to VSS.
AMPS_CTL 8 O Automatic MPS control. Connect a resistor with appropriate power rating (to support the MPS current) from AMPS_CTL to VSS to program the MPS current amplitude. Leave AMPS_CTL open to disable the automatic MPS function.
MPS_DUTY 9 I MPS duty cycle select input, referenced to VSS, internally driven by a precision current source with voltage limited to less than ~5.5V. A resistor connected to VSS determines if the MPS duty cycle selected is either 5.4% (open), 8.1% (~60.4 kΩ) or 12.5% (short).
APD 10 I Auxiliary power detect input. Raise 1.65 V above RTN to disable pass MOSFET, to force TPH active (low) and to force TPL and /BT inactive (open). If not used, connect APD to RTN.
RTN 11, 12 — Drain of PoE pass MOSFET. Return line from the load to the controller.
PG 13 O Power Good output. Open-drain, active-high output referenced to RTN.
VC_OUT 14 O VC output. Connect to the low voltage supply pin of the PWM controller. Bypass with a 1 µF to RTN in most applications. If the applications requires operations from a 12 V adapter, a higher capacitance value is needed.
VC_IN 15 I VC input. Connect to auxiliary bias voltage source, usually derived from an auxiliary winding of the power transformer of the converter. Bypass with a 0.1 µF to RTN.
UVLO_SEL 16 I UVLO select, referenced to RTN, internally pulled-up to 5.5 V internal rail. Leave open when the selected PWM has a falling UVLO above 7.25V. Pull UVLO_SEL low if it is between 4.25V and 7.25V.
TPL 17 O PSE allocated power outputs, binary coded. Open-drain, active-low outputs referenced to RTN. TPL becomes open and TPH pulls low if an auxiliary power adapter is detected via the APD input.
TPH 18 O
BT 19 O Indicates that a PSE applying an IEEE802.3bt (Type 3 or 4) mutual identification scheme has been identified. Open-drain, active-low output referenced to RTN. /BT becomes open if an auxiliary power adapter is detected.
NC 20 — No connect pin. Leave open.
Pad — — The exposed thermal pad must be connected to VSS. A large fill area is required to assist in heat dissipation.