JAJSJS0A June   2020  – September 2020 TPS23734

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: DC-DC Controller Section
    6. 7.6 Electrical Characteristics PoE
    7.     15
    8. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  CLS Classification
      2. 8.3.2  DEN Detection and Enable
      3. 8.3.3  APD Auxiliary Power Detect
      4. 8.3.4  Internal Pass MOSFET
      5. 8.3.5  T2P and APDO Indicators
      6. 8.3.6  DC-DC Controller Features
        1. 8.3.6.1 VCC, VB, VBG and Advanced PWM Startup
        2.       28
        3. 8.3.6.2 CS, Current Slope Compensation and blanking
        4. 8.3.6.3 COMP, FB, EA_DIS, CP, PSRS and Opto-less Feedback
        5. 8.3.6.4 FRS Frequency Setting and Synchronization
        6. 8.3.6.5 DTHR and Frequency Dithering for Spread Spectrum Applications
        7. 8.3.6.6 SST and Soft-Start of the Switcher
        8. 8.3.6.7 SST, I_STP, LINEUV and Soft-Stop of the Switcher
      7. 8.3.7  Switching FET Driver - GATE, GTA2, DT
      8. 8.3.8  EMPS and Automatic MPS
      9. 8.3.9  VDD Supply Voltage
      10. 8.3.10 RTN, AGND, GND
      11. 8.3.11 VSS
      12. 8.3.12 Exposed Thermal pads - PAD_G and PAD_S
    4. 8.4 Device Functional Modes
      1. 8.4.1  PoE Overview
      2. 8.4.2  Threshold Voltages
      3. 8.4.3  PoE Start-Up Sequence
      4. 8.4.4  Detection
      5. 8.4.5  Hardware Classification
      6. 8.4.6  Maintain Power Signature (MPS)
      7. 8.4.7  Advanced Start-Up and Converter Operation
      8. 8.4.8  Line Undervoltage Protection and Converter Operation
      9. 8.4.9  PD Self-Protection
      10. 8.4.10 Thermal Shutdown - DC-DC Controller
      11. 8.4.11 Adapter ORing
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1  Input Bridges and Schottky Diodes
          2. 9.2.1.1.2  Input TVS Protection
          3. 9.2.1.1.3  Input Bypass Capacitor
          4. 9.2.1.1.4  Detection Resistor, RDEN
          5. 9.2.1.1.5  Classification Resistor, RCLS.
          6. 9.2.1.1.6  Dead Time Resistor, RDT
          7. 9.2.1.1.7  APD Pin Divider Network, RAPD1, RAPD2
          8. 9.2.1.1.8  Setting Frequency (RFRS) and Synchronization
          9. 9.2.1.1.9  Bias Supply Requirements and CVCC
          10. 9.2.1.1.10 APDO, T2P Interface
          11. 9.2.1.1.11 Secondary Soft Start
          12. 9.2.1.1.12 Frequency Dithering for Conducted Emissions Control
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 EMI Containment
    4. 11.4 Thermal Considerations and OTSD
    5. 11.5 ESD
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Adapter ORing

Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power solution adds cost and complexity, but allows a product to be used if PoE is not available in a particular installation. While most applications only require that the PD operate when both sources are present, the TPS23734 device supports forced operation from either of the power sources. Figure 8-15 illustrates three options for diode ORing external power into a PD. Only one option would be used in any particular design. Option 1 applies power to the device input, option 2 applies power between the device PoE section and the power circuit, and option 3 applies power to the output side of the converter. Each of these options has advantages and disadvantages. A detailed discussion of the device and ORing solutions is covered in application note Advanced Adapter ORing Solutions using the TPS23753, (SLVA306).

GUID-9296945E-2B90-4DEC-8179-AB547E55BCE8-low.gifFigure 8-15 ORing Configurations

Preference of one power source presents a number of challenges. Combinations of adapter output voltage (nominal and tolerance), power insertion point, and which source is preferred determine solution complexity. Several factors contributing to the complexity are the natural high-voltage selection of diode ORing (the simplest method of combining sources), the current limit implicit in the PSE, PD inrush, and protection circuits (necessary for operation and reliability). Creating simple and seamless solutions is difficult if not impossible for many of the combinations. However, the TPS23734 device offers several built-in features that simplify some combinations.

Several examples demonstrate the limitations inherent in ORing solutions. Diode ORing a 48-V adapter with PoE (option 1) presents the problem that either source may have the higher voltage. A blocking switch would be required to assure that one source dominates. A second example is combining a 12-V adapter with PoE using option 2. The converter draws approximately four times the current at 12 V from the adapter than it does from PoE at 48 V. Transition from adapter power to PoE may demand more current than can be supplied by the PSE. The converter must be turned off while CIN capacitance charges, with a subsequent converter restart at the higher voltage and lower input current. A third example is use of a 24-V adapter with ORing option 1. The PD hotswap would have to handle two times the current, and have 1/4 the resistance (be 4 times larger) to dissipate equal power.

The most popular preferential ORing scheme is option 2 with adapter priority. The hotswap MOSFET is disabled when the adapter is used to pull APD high, blocking the PoE source from powering the output. This solution works well with a wide range of adapter voltages, is simple, and requires few external parts. When the AC power fails, or the adapter is removed, the hotswap switch is enabled. In the simplest implementation, the PD momentarily loses power until the PSE completes its start-up cycle.

The DEN pin can be used to disable the PoE input when ORing with option 3. This is an adapter priority implementation. Pulling DEN low, while creating an invalid detection signature, disables the hotswap MOSFET, and prevents the PD from redetecting. This would typically be accomplished with an optocoupler that is driven from the secondary side of the converter. Another option 3 alternative which does not require DEN optocoupler is achievable by ensuring that the auxiliary voltage is always higher then the converter output; in this case, the PSE power can then be maintained by use of the auto MPS function of the TPS23734.

The IEEE standards require that the PI conductors be electrically isolated from ground and all other system potentials not part of the PI interface. The adapter must meet a minimum 1500-Vac dielectric withstand test between the output and all other connections for options 1 and 2. The adapter only needs this isolation for option 3 if it is not provided by the converter.

Adapter ORing diodes are shown for all the options to protect against a reverse-voltage adapter, a short on the adapter input pins, and damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET in option 3.