The current-sense input for the DC-DC converter should be connected to the high side of the current-sense resistor of the switching MOSFET. This voltage drives the current limit comparator and the PWM comparator (see Block Diagram of DC-DC controller). A leading-edge blanking circuit prevents MOSFET turn-on transients from falsely triggering either of these comparators. During the off time, and also during the blanking time that immediately follows, the CS pin is pulled to AGND through an internal pulldown resistor.

The current limit comparator terminates the on-time portion of the switching cycle as soon as V_CS exceeds approximately 250 mV (V_CSMAX) and the leading edge blanking interval has expired. If the converter is not in current limit, then either the PWM comparator or the maximum duty cycle limiting (D_MAX) circuit terminates the on time.

Current-mode control requires addition of a compensation ramp to the sensed inductive (transformer or inductor) current for stability at duty cycles near and over 50%. The TPS23734 provides an internal slope compensation circuit which generates a current that imposes a voltage ramp at the positive input of the PWM comparator to suppress sub-harmonic oscillations. This current flows out of the CS pin. If desired, the magnitude of the slope compensation can be increased by the addition of an external resistor R_S (see Figure 8-2) in series with the CS pin. It works with ramp current (I_PK = I_SL-EX, approximately 20 μA) that flows out of the CS pin when the MOSFET is on. The I_PK specification does not include the approximately 2-μA fixed current that flows out of the CS pin.

The TPS23734 has a maximum duty cycle limit of 78%, permitting the design of wide input-range converters with a lower voltage stress on the output rectifiers. While the maximum duty cycle is 78%, converters may be designed that run at duty cycles well below this for a narrower, 36-V to 57-V range.

Most current-mode control papers and application notes define the slope compensation values in terms of V_PP/T_S (peak ramp voltage / switching period); however, Electrical Characteristics: DC-DC Controller Section specifies the slope peak (V_SLOPE) based on the maximum duty cycle. Assuming that the desired slope, V_SLOPE-D (in mV/period), is based on the full period, compute R_S per Equation 1 where V_SLOPE, D_MAX, and I_SL-EX are from Electrical Characteristics: DC-DC Controller Section with voltages in mV, current in μA, and the duty cycle is unitless (for example, D_MAX = 0.78).

Equation 1.

Figure 8-2 Additional Slope Compensation

The TPS23734 blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This avoids current-sense waveform distortion, which tends to get worse at light output loads. There may be some situations or designers that prefer an R-C approach, for example if the presence of R_S causes increased noise, due to adjacent noisy signals, to appear at CS pin. The TPS23734 provides a pulldown on CS (~400 Ω) during the GATE OFF-time to improve sensing when an R-C filter must be used, by reducing cycle-to-cycle carry-over voltage on C_S.

Routing between the current-sense resistor and the CS pin should be short to minimize cross-talk from noisy traces such as the gate drive signal and the CP signal.