JAJSEO4E July   2012  – January 2018 TPS23751 , TPS23752

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings: Surge
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electric Characteristics - Controller Section
    7. 6.7 Electrical Characteristics - Sleep Mode (TPS23752 Only)
    8. 6.8 Electrical Characteristics - PoE Interface Section
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Pin Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 PoE Overview
        1. 7.4.1.1 Threshold Voltages
        2. 7.4.1.2 PoE Startup Sequence
        3. 7.4.1.3 Detection
        4. 7.4.1.4 Hardware Classification
        5. 7.4.1.5 Inrush and Startup
        6. 7.4.1.6 Maintain Power Signature
        7. 7.4.1.7 Startup and Converter Operation
        8. 7.4.1.8 PD Hotswap Operation
      2. 7.4.2 Sleep Mode Operation (TPS23752 only)
        1. 7.4.2.1  Converter Controller Features
        2. 7.4.2.2  PWM and VFO Operation; CTL, SRT, and SRD Pin Relationships to Output Load Current
        3. 7.4.2.3  Bootstrap Topology
        4. 7.4.2.4  Current Slope Compensation and Current Limit
        5. 7.4.2.5  RT
        6. 7.4.2.6  T2P, Startup and Power Management
        7. 7.4.2.7  Thermal Shutdown
        8. 7.4.2.8  Adapter ORing
        9. 7.4.2.9  Using DEN to Disable PoE
        10. 7.4.2.10 ORing Challenges
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistor, RCLS
        6. 8.2.2.6  APD Pin Divider Network, RAPD1, RAPD2
        7. 8.2.2.7  Setting the PWM-VFO Threshold using the SRT pin
        8. 8.2.2.8  Setting Frequency (RT)
        9. 8.2.2.9  Current Slope Compensation
        10. 8.2.2.10 Voltage Feed-Forward Compensation
        11. 8.2.2.11 Estimating Bias Supply Requirements and Cvc
        12. 8.2.2.12 Switching Transformer Considerations and RVC
        13. 8.2.2.13 T2P Pin Interface
        14. 8.2.2.14 Softstart
        15. 8.2.2.15 Special Switching MOSFET Considerations
        16. 8.2.2.16 ESD
        17. 8.2.2.17 Thermal Considerations and OTSD
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
      2. 11.1.2 関連リンク
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Electrical Characteristics - Sleep Mode (TPS23752 Only)

Unless otherwise noted, 40 V ≤ VDD ≤ 57 V; VCTL = VMODE = VSLPb = VB; VSRT = 0.5 V; VAPD = VCS = VARTN = VRTN; CLS, GATE, LED, SRD, T2P open; RWAKE = 392 kΩ; RDEN = 24.9 kΩ; RT = 34 kΩ; CVB = CVC = 0.1 µF;
–40 ≤ TJ ≤ 125°C. Typical values are at 25°C. All voltages referred to VSS.
VDD = 48 V, VAPD = VARTN = VRTN = VVSS, VVC = 13 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SLPb
SLPb threshold VSLPb falling until ILED↑ 1.10 1.66 2.10 V
Input pullup current 4 5.7 8 µA
MODE
MODE threshold MODE falling unti ILED ↑ 1.10 1.66 2.10 V
MODE hysteresis (1) 1.6 V
Input pullup current 4 5.7 8 µA
WAKE
Output voltage Sleep mode 2.43 2.50 2.57 V
RWKPLUP Pull-up resistance 3.95 5.33 6.88 kΩ
LED
Output low voltage SLPb ↓, ILED = 10 mA 0.60 0.90 1.50 V
Leakage current VLED = 18 V 10 µA
SLEEP SUPPLY CURRENT
Sleep supply current when APD is enabled VAPD = 2 V; SLPb ↓, measure IVDD 0.5 1 mA
MPS supply current Pulsed mode: VMODE = 0 V; SLPb ↓,
Measure IVDD 0 ≤ ILED ≤ 10 mA		 10.0 10.6 11.5 mApk
DC mode: VMODE = VB, then SLPb ↓,
Measure IVDD 0 ≤ ILED ≤ 10 mA		 10.0 10.6 11.5 mA
MPS pulsed mode duty cycle MPS pulsed current duty cycle 28.80% 28.88% 28.95%
MPS pulsed current ON time 75 87.5 ms
MPS pulsed current OFF time 215 250 ms
(1) Parameters provided for reference only, and do not constitute part of TI published specifications for purposes of TI product warranty.