8.4.1.13 Dead Time

The TPS23754 device features two switching MOSFET gate drivers to ease implementation of high-efficiency topologies. Specifically, these include active (primary) clamp topologies and those with synchronous drivers that are hard-driven by the control circuit. In all cases, there is a need to assure that both driven MOSFETs are not on at the same time. The DT pin programs a fixed time period delay between the turnon of one gate driver until the turnon of the next. This feature is an improvement over the repeatability and accuracy of discrete solutions while eliminating a number of discrete parts on the board. Converter efficiency is easily tuned with this one repeatable adjustment. The programmed dead time is the same for both GATE-to-GAT2 and GAT2-to-GATE transitions. The dead time is triggered from internal signals that are several stages back in the driver to eliminate the effects of gate loading on the period; however, the observed and actual dead-time will be somewhat dependent on the gate loading. The turnoff of GAT2 coincides with the start of the internal clock period.

DT may be used to disable GAT2, which goes to a high-impedance state.

GATE’s phase turns the main switch on when it transitions high, and off when it transitions low. GAT2’s phase turns the second switch off when it transitions high, and on when it transitions low. Both switches should be off when GAT2 is high and GATE is low. The signal phasing is shown in Figure 1. Many topologies that use secondary-side synchronous rectifiers also use N-Channel MOSFETs driven through a gate-drive transformer. The proper signal phase for these rectifiers may be achieved by inverting the phasing of the secondary winding (swapping the leads). Use of the two gate drives is shown in Figure 27 and Figure 27.