11.1 Layout Guidelines

The layout of the PoE front end must use good practices for power and EMI/ESD. A basic set of recommendations include:

1. The parts placement must be driven by the power flow in a point-to-point manner such as RJ-45 → Ethernet interface → diode bridges → TVS and 0.1-μF capacitor → TPS2376-H → output capacitor.
2. There should not be any crossovers of signals from one part of the flow to another.
3. All leads should be as short as possible with wide power traces and paired signal and return.
4. Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage rails and between the input and an isolated converter output.
5. The TPS2376-H should be over a local ground plane or fill area referenced to VSS.
6. Large SMT component pads should be used on power dissipating devices such as the diodes and the TPS2376-H.

Use of generous copper area on VSS and to help the PCB spread and dissipate the heat is recommended. Assuming a worst-case power dissipation of 0.4 W, the required thermal resistance may be calculated as: θ_JA = ( t_{J_MAX} - t_{A_MAX} ) / P. A thermal resistance of 50°C/W is required for a junction temperature of 105°C at an ambient of 85°C. The effect of additional local heating on the circuit board from other devices must be considered. The thermal resistance cases provided in the dissipation rating table should be used as a guide in determining the required area.

The Layout Example provides an example of a single sided layout with liberal copper plane areas to help spread the heat. The active circuit area could be reduced by locating the small resistors on the backside of the board. The TPS2376-H PowerPad is covered by copper fill, which has multiple vias to a backside mirror-image fill. There are 5 small vias under the PowerPad per the guidelines of SLMA0002 which are masked by the graphics of the tool. The fills for RTN and VDD also help spread the heat. A copper fill clearance of 0.030 inches was used for VDD to RTN or VSS. A spacing of 0.025 inches for the full PoE voltage was met elsewhere.