SLVSB99C March   2012  – July 2015 TPS2378

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  APD Auxiliary Power Detect
      2. 7.3.2  CDB Converter Disable Bar Pin Interface
      3. 7.3.3  CLS Classification
      4. 7.3.4  DEN Detection and Enable
      5. 7.3.5  Internal Pass MOSFET
      6. 7.3.6  T2P Type-2 PSE Indicator
      7. 7.3.7  VDD Supply Voltage
      8. 7.3.8  VSS
      9. 7.3.9  PowerPAD
      10. 7.3.10 Forced, Four-Pair, High Power PoE
    4. 7.4 Device Functional Modes
      1. 7.4.1  PoE Overview
      2. 7.4.2  Threshold Voltages
      3. 7.4.3  PoE Start-up Sequence
      4. 7.4.4  Detection
      5. 7.4.5  Hardware Classification
      6. 7.4.6  Inrush and Start-up
      7. 7.4.7  Maintain Power Signature
      8. 7.4.8  Start-up and Converter Operation
      9. 7.4.9  PD Hotswap Operation
      10. 7.4.10 Start-up and Power Management, CDB and T2P
      11. 7.4.11 Adapter ORing
      12. 7.4.12 Using DEN to Disable PoE
      13. 7.4.13 ORing Challenges
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Requirements
        1. 8.2.2.1 Input Bridges and Schottky Diodes
        2. 8.2.2.2 Protection, D1
        3. 8.2.2.3 Capacitor, C1
        4. 8.2.2.4 Detection Resistor, RDEN
        5. 8.2.2.5 Classification Resistor, RCLS
        6. 8.2.2.6 APD Pin Divider Network RAPD1, RAPD2
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 EMI Containment
    4. 10.4 Thermal Considerations and OTSD
    5. 10.5 ESD
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DDA Package
8-Pin HSOP
Top View
TPS2378 po_lvsb99.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
VDD 1 I Connect to positive PoE input power rail. Bypass with 0.1 µF to VSS.
DEN 2 I/O Connect 24.9 kΩ to VDD for detection. Pull to VSS disable pass MOSFET.
CLS 3 O Connect resistor from CLS to VSS to program classification current.
VSS 4 — Connect to negative power rail derived from PoE source.
RTN 5 — Drain of PoE pass MOSFET.
CDB 6 O Active low, open-drain converter disable output, referenced to RTN.
T2P 7 O Active low indicates type 2 PSE connected or APD active.
APD 8 I Raise 1.5 V above RTN to disable pass MOSFET and force T2P active.
Pad — — The PowerPad™ must be connected to VSS. A large fill area is required to assist in heat dissipation.