JAJSHI3C March   2019  – October 2019 TPS23881

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
    2. 7.1 Detailed Pin Description
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Timing Diagrams
  10. 10Detailed Description
    1. 10.1 Overview
      1. 10.1.1 Operating Modes
        1. 10.1.1.1 Auto
        2. 10.1.1.2 Autonomous
        3. 10.1.1.3 Semiauto
        4. 10.1.1.4 Manual/Diagnostic
        5. 10.1.1.5 Power Off
      2. 10.1.2 Channel versus Port Terminology
      3. 10.1.3 Requested Class versus Assigned Class
      4. 10.1.4 Power Allocation and Power Demotion
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Port Remapping
      2. 10.3.2 Port Power Priority
      3. 10.3.3 Analog-to-Digital Converters (ADC)
      4. 10.3.4 I2C Watchdog
      5. 10.3.5 Current Foldback Protection
    4. 10.4 Device Functional Modes
      1. 10.4.1 Detection
      2. 10.4.2 Connection Check
      3. 10.4.3 Classification
      4. 10.4.4 DC Disconnect
    5. 10.5 I2C Programming
      1. 10.5.1 I2C Serial Interface
    6. 10.6 Register Maps
      1. 10.6.1 Complete Register Set
      2. 10.6.2 Detailed Register Descriptions
        1. 10.6.2.1  INTERRUPT Register
          1. Table 5. INTERRUPT Register Field Descriptions
        2. 10.6.2.2  INTERRUPT MASK Register
          1. Table 6. INTERRUPT MASK Register Field Descriptions
        3. 10.6.2.3  POWER EVENT Register
          1. Table 7. POWER EVENT Register Field Descriptions
        4. 10.6.2.4  DETECTION EVENT Register
          1. Table 8. DETECTION EVENT Register Field Descriptions
        5. 10.6.2.5  FAULT EVENT Register
          1. Table 9. FAULT EVENT Register Field Descriptions
        6. 10.6.2.6  START/ILIM EVENT Register
          1. Table 10. START/ILIM EVENT Register Field Descriptions
        7. 10.6.2.7  SUPPLY and FAULT EVENT Register
          1. Table 11.  SUPPLY and FAULT EVENT Register Field Descriptions
          2. 10.6.2.7.1 Detected SRAM Faults and "Safe Mode"
            1. 10.6.2.7.1.1 ULA (Ultra Low Alpha) Package Option: TPS23881A
        8. 10.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 10.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 10.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 10.6.2.11 CHANNEL 4 DISCOVERY Register
          1. Table 12. CHANNEL n DISCOVERY Register Field Descriptions
        12. 10.6.2.12 POWER STATUS Register
          1. Table 13. POWER STATUS Register Field Descriptions
        13. 10.6.2.13 PIN STATUS Register
          1. Table 14.   PIN STATUS Register Field Descriptions
          2. 10.6.2.13.1 AUTONOMOUS MODE
        14. 10.6.2.14 OPERATING MODE Register
          1. Table 16. OPERATING MODE Register Field Descriptions
        15. 10.6.2.15 DISCONNECT ENABLE Register
          1. Table 20. DISCONNECT ENABLE Register Field Descriptions
        16. 10.6.2.16 DETECT/CLASS ENABLE Register
          1. Table 21. DETECT/CLASS ENABLE Register Field Descriptions
        17. 10.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
          1. Table 22. Power Priority / 2P-PCUT Disable Register Field Descriptions
        18. 10.6.2.18 TIMING CONFIGURATION Register
          1. Table 24. TIMING CONFIGURATION Register Field Descriptions
        19. 10.6.2.19 GENERAL MASK Register
          1. Table 25. GENERAL MASK Register Field Descriptions
        20. 10.6.2.20 DETECT/CLASS RESTART Register
          1. Table 27. DETECT/CLASS RESTART Register Field Descriptions
        21. 10.6.2.21 POWER ENABLE Register
          1. Table 28. POWER ENABLE Register Field Descriptions
        22. 10.6.2.22 RESET Register
          1. Table 32. RESET Register Field Descriptions
        23. 10.6.2.23 ID Register
          1. Table 34. ID Register Field Descriptions
        24. 10.6.2.24 Connection Check and Auto Class Status Register
          1. Table 35. Connection Check and Auto Class Field Descriptions
        25. 10.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 10.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 10.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 10.6.2.28 2-Pair Police Ch-4 Configuration Register
          1. Table 36. 2-Pair Policing Register Fields Descriptions
        29. 10.6.2.29 Capacitance (Legacy PD) Detection
          1. Table 39. Capacitance Detection Register Field Descriptions
        30. 10.6.2.30 Power-on Fault Register
          1. Table 40. Power-on Fault Register Field Descriptions
        31. 10.6.2.31 PORT RE-MAPPING Register
          1. Table 41. PORT RE-MAPPING Register Field Descriptions
        32. 10.6.2.32 Channels 1 and 2 Multi Bit Priority Register
        33. 10.6.2.33 Channels 3 and 4 Multi Bit Priority Register
          1. Table 42. Channels n MBP Register Field Descriptions
        34. 10.6.2.34 4-Pair Wired and Port Power Allocation Register
          1. Table 44. 4-Pair Wired and Power Allocation Register Field Descriptions
        35. 10.6.2.35 4-Pair Police Ch-1 and 2 Configuration Register
        36. 10.6.2.36 4-Pair Police Ch-3 and 4 Configuration Register
          1. Table 46. 4-Pair Police Register Field Descriptions
        37. 10.6.2.37 TEMPERATURE Register
          1. Table 48. TEMPERATURE Register Field Descriptions
        38. 10.6.2.38 4-Pair Fault Configuration Register
          1. Table 49. 4-Pair Fault Register Field Descriptions
        39. 10.6.2.39 INPUT VOLTAGE Register
          1. Table 50. INPUT VOLTAGE Register Field Descriptions
        40. 10.6.2.40 CHANNEL 1 CURRENT Register
        41. 10.6.2.41 CHANNEL 2 CURRENT Register
        42. 10.6.2.42 CHANNEL 3 CURRENT Register
        43. 10.6.2.43 CHANNEL 4 CURRENT Register
          1. Table 51. CHANNEL n CURRENT Register Field Descriptions
        44. 10.6.2.44 CHANNEL 1 VOLTAGE Register
        45. 10.6.2.45 CHANNEL 2 VOLTAGE Register
        46. 10.6.2.46 CHANNEL 3 VOLTAGE Register
        47. 10.6.2.47 CHANNEL 4 VOLTAGE Register
          1. Table 52. CHANNEL n VOLTAGE Register Field Descriptions
        48. 10.6.2.48 2x FOLDBACK SELECTION Register
          1. Table 53. 2x FOLDBACK SELECTION Register Field Descriptions
        49. 10.6.2.49 FIRMWARE REVISION Register
          1. Table 54. FIRMWARE REVISION Register Field Descriptions
        50. 10.6.2.50 I2C WATCHDOG Register
          1. Table 55. I2C WATCHDOG Register Field Descriptions
        51. 10.6.2.51 DEVICE ID Register
          1. Table 57. DEVICE ID Register Field Descriptions
        52. 10.6.2.52 CHANNEL 1 DETECT RESISTANCE Register
        53. 10.6.2.53 CHANNEL 2 DETECT RESISTANCE Register
        54. 10.6.2.54 CHANNEL 3 DETECT RESISTANCE Register
        55. 10.6.2.55 CHANNEL 4 DETECT RESISTANCE Register
          1. Table 58. DETECT RESISTANCE Register Fields Descriptions
        56. 10.6.2.56 CHANNEL 1 DETECT CAPACITANCE Register
        57. 10.6.2.57 CHANNEL 2 DETECT CAPACITANCE Register
        58. 10.6.2.58 CHANNEL 3 DETECT CAPACITANCE Register
        59. 10.6.2.59 CHANNEL 4 DETECT CAPACITANCE Register
          1. Table 59. DETECT CAPACITANCE Register Fields Descriptions
        60. 10.6.2.60 CHANNEL 1 ASSIGNED CLASS Register
        61. 10.6.2.61 CHANNEL 2 ASSIGNED CLASS Register
        62. 10.6.2.62 CHANNEL 3 ASSIGNED CLASS Register
        63. 10.6.2.63 CHANNEL 4 ASSIGNED CLASS Register
          1. Table 60. CHANNEL n ASSIGNED CLASS Register Field Descriptions
        64. 10.6.2.64 AUTO CLASS CONTROL Register
          1. Table 63. AUTO CLASS CONTROL Register Field Descriptions
        65. 10.6.2.65 CHANNEL 1 AUTO CLASS POWER Register
        66. 10.6.2.66 CHANNEL 2 AUTO CLASS POWER Register
        67. 10.6.2.67 CHANNEL 3 AUTO CLASS POWER Register
        68. 10.6.2.68 CHANNEL 4 AUTO CLASS POWER Register
          1. Table 65. AUTO CLASS POWER Register Fields Descriptions
        69. 10.6.2.69 ALTERNATIVE FOLDBACK Register
          1. Table 66. ALTERNATIVE FOLDBACK Register Field Descriptions
        70. 10.6.2.70 SRAM CONTROL Register
          1. Table 67. SRAM CONTROL Register Field Descriptions
        71. 10.6.2.71 SRAM START ADDRESS (LSB) Register
        72. 10.6.2.72 SRAM START ADDRESS (MSB) Register
          1. Table 68. SRAM START ADDRESS Register Field Descriptions
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Autonomous Operation
      2. 11.1.2 Introduction to PoE
        1. 11.1.2.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
      3. 11.1.3 SRAM Programming
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Connections on Unused Channels
        2. 11.2.2.2 Power Pin Bypass Capacitors
        3. 11.2.2.3 Per Port Components
        4. 11.2.2.4 System Level Components (not shown in the schematic diagrams)
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
    1. 12.1 VDD
    2. 12.2 VPWR
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Kelvin Current Sensing Resistors
    2. 13.2 Layout Example
      1. 13.2.1 Component Placement and Routing Guidelines
        1. 13.2.1.1 Power Pin Bypass Capacitors
        2. 13.2.1.2 Per-Port Components
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 ドキュメントのサポート
      1. 14.1.1 関連資料
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 サポート・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.6.2.21 POWER ENABLE Register

COMMAND = 19h with 1 Data Byte, Write Only

Push button register.

Used to initiate a channel(s) turn on or turn off in any mode except OFF mode.

Figure 65. POWER ENABLE Register Format
7 6 5 4 3 2 1 0
POFF4 POFF3 POFF2 POFF1 PWON4 PWON3 PWON2 PWON1
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 28. POWER ENABLE Register Field Descriptions

Bit Field Type Reset Description
7–4 POFF4–POFF1 W 0 Channel power off bits
3–0 PWON4–PWON1 W 0 Channel power on bits

SPACE

NOTE

Writing a “1” at POFFn and PWONn on same Channel during the same write operation turns the Channel off.

NOTE

The tOVLD, tLIM, tSTART and disconnect events have priority over the PWON command. During tOVLD, tLIM or tSTART, cool down cycle, any channel turn on using Power Enable command will be ignored and the Channel will be kept off.

NOTE

For 4-Pair wired ports:

These bits control the individual Channel response of each Channel. Thus it is recommended that for 4-pair wire ports, the bits for both channels be set simultaneously.

In Semi Auto mode with DETE = CLE = 1 on both channels, it is permissible to set only one PWON bit to attempt to turn on only that singular channel.

For 4P Single Signature devices that classify as class 5-8, a singular PWON command will fail and a STRT fault set with the “insufficient power” code written to 0x24.

If the PD presents itself as class 4 or below, then only that pair set will be powered.

Setting the alternate PWON bit for the secondary channel of a single signature device after the primary is already powered will result in the immediate turn on of the channel without completing DET or CLS.

For a 4-Pair Dual Signature device that has only one channel powered, setting the PWON bit for the unpowered channel will result in a turn on attempt on that channel based on the assigned classification of the other channel and the Power Allocation settings in 0x29h at the time of the new PWON command.

PWONn in Diagnostic/Manual Mode:

If the PSE controller is configured in Diagnostic mode, writing a “1” at that PWONn bit location will immediately turn on the associated Channel.

SPACE

PWONn in Semi Auto Mode:

While in Semi Auto mode, writing a “1” at a PWONn bit will attempt to turn on the associated Channel. If the detection or class results are invalid, the Channel is not turned on, and there will be no additional attempts to turn on the Channel until this push button is reasserted and the channel will resume its configured semi auto mode operation.

NOTE

In Semi Auto mode, the Power Allocation (0x29h) value needs to be set prior to issuing a PWON command. Any changes to the Power Allocation value after a PWON command is given may be ignored.

Table 29. Channel Response to PWONn Command in Semi Auto Mode

CLEn DETEn Channel Operation Result of PWONn Command
0 0 Idle Singular Turn On attempted with Full DET and CLS cycle
0 1 Cycling Detection Measurements only Singular Turn On attempted with Full DET and CLS cycle
1 0 Idle Singular Turn On attempted with Full DET and CLS cycle
1 1 Cycling Detection and Classification Measurements Singular Turn On attempted after next (or current) DET and CLS cycle

In semi auto mode with DETE and CLE set, as long as the PWONx command is received prior to the start of classification, the Channel will be powered immediately after classification is complete provided the classification result is valid and the power allocations settings (see register 0x29h) are sufficient to enable power on.

SPACE

PWONn in Auto Mode:

In Auto mode with DETE or CLE set to 0, a PWONx command will initiate a singular detection and classification cycle and the port/channel will be powered immediately after classification is complete provided the classification result is valid and the power allocations settings (see register 0x29h) are sufficient to enable power on.

In Auto mode with DETE and CLE = 1, there is no need for a PWON command. The port/channel will automatically attempt to turn on after each detection and classification cycle.

NOTE

In Auto mode, the Power Allocation (0x29h) value needs to be set prior to issuing a PWON command. Any changes to the Power Allocation value after a PWON command is given may be ignored.

A singular PWONn command will be ignored for a 4-Pair wired port in Auto mode.

Table 30. Channel Response to PWONn Command in Auto Mode

CLEn DETEn Channel Operation Result of PWONn Command
0 0 Idle Singular Turn On attempted with Full DET and CLS cycle
0 1 Cycling Detection Measurements only Singular Turn On attempted with Full DET and CLS cycle
1 0 Idle Singular Turn On attempted with Full DET and CLS cycle
1 1 Cycling Detection and Classification Measurements NA - Channel will power automatically after a valid detection and classification

PWOFFn in any Mode:

The channel is immediately disabled and the following registers are cleared:

Table 31. Channel Turn Off with PWOFFn Command

Register Bits to be Reset
0x04 CLSCn and DETCn
0x06 DISFn and PCUTn
0x08 STRTn and ILIMn
0x0A/B PCUTnn
0x0C-0F Requested Class and Detection
0x10 PGn and PEn
0x14 CLEn and DETEn
0x1C ACn and CCnn
0x1E-21 2P Policing set to 0xFFh
0x24 PFn
0x2A-2B 4P Policing set to 0xFFh
0x2D NLMnn, NCTnn, 4PPCTnn, and DCDTnn
0x30-3F Channel Voltage and Current Measurements
0x40 2xFBn
0x44 - 47 Detection Resistance Measurements
0x4C-4F Assigned Class and Previous Class
0x51-54 Autoclass Measurement

NOTE

It may take upwards of 5ms after PWOFFn command for all register values to be updated.

Only the bits associated with the channel/port ("n") with PWOFFn set will be cleared. Those bits associated with channels/ports remaining in operation will not be changed.

These bits control the response of each channel individually. Thus, it is recommended that for 4-pair wire ports, the bits for both channels be set simultaneously.

NOTE

If only one channel of a 4-pair single signature load with a Class 5 or higher assigned class is given a PWOFFn command, both channels will be disabled.

In the event a singular channel of a 4-pair dual signature PD is turned off due to a PWOFFn command, the power may be reapplied to that channel by setting the PWON bit in 0x19h provided the detection and classification are still valid and the Power Allocation settings in 0x29 are sufficient based on the assigned classification of the powered channel.