JAJS232E November   2006  – October 2019 TPS2410 , TPS2411

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
    1.     Pin Functions, PW
    2.     Pin Functions, RMS
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics: TPS2410, 11
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Device Pins
        1. 9.3.1.1  A, C:
        2. 9.3.1.2  BYP:
        3. 9.3.1.3  FLTR:
        4. 9.3.1.4  FLTB:
        5. 9.3.1.5  GATE:
        6. 9.3.1.6  GND:
        7. 9.3.1.7  RSET:
        8. 9.3.1.8  RSVD:
        9. 9.3.1.9  STAT
        10. 9.3.1.10 UV, OV, PG:
        11. 9.3.1.11 VDD:
      2. 9.3.2 Gate Drive, Charge Pump and C(BYP)
      3. 9.3.3 Fast Comparator Input Filtering – C(FLTR)
      4. 9.3.4 UV, OV, and PG
      5. 9.3.5 Input ORing and Stat
    4. 9.4 Device Functional Modes
      1. 9.4.1 TPS2410 vs TPS2411 – MOSFET Control Methods
  10. 10Application and Implementation
    1. 10.1 Typical Connections
      1. 10.1.1 N+1 Power Supply
      2. 10.1.2 Input ORing
    2. 10.2 Typical Application Examples
      1. 10.2.1 VDD, BYP, and Powering Options
      2. 10.2.2 Bidirectional Blocking and Protection of C
      3. 10.2.3 ORing Examples
      4. 10.2.4 Design Requirements
        1. 10.2.4.1 MOSFET Selection and R(RSET)
        2. 10.2.4.2 TPS2410 Regulation-loop Stability
      5. 10.2.5 Detailed Design Procedure
      6. 10.2.6 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Recommended Operating Range
    2. 11.2 System Design and Behavior with Transients
  12. 12Layout
    1. 12.1 Layout Considerations
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

7 Pin Configuration and Functions

PW Package
TSSOP 14 Pin
Top View

Pin Functions, PW

PIN I/O DESCRIPTION
NAME NO.
VDD 1 PWR Input power for the gate drive charge pump and internal controls. VDD must be connected to a supply voltage ≥ 3 V.
RSET 2 I Connect a resistor to ground to program the turn-off threshold. Leaving RSET open results in a slightly positive V(A-C) turn-off threshold.
STAT 3 I/O STAT is a multifunction pin. A high output indicates that the MOSFET gate is being driven high. Overdriving STAT low while GATE is high shifts the fast-turnoff threshold negative. STAT has a weak pull-up to VDD.
FLTB 4 O Open drain fault output. Fault is active (low) for any of the following conditions:
  • Insufficient VDD
  • GATE should be high but is not.
  • The MOSFET should be ON but the forward voltage exceeds 0.4 V.
OV 5 I OV is a voltage monitor that contributes to the PG output, and also causes the MOSFET to turn off if it is above the 0.6-V threshold. OV is programmable via an external resistor divider. An OV voltage above 0.6 V indicates a bus voltage that is too high.
UV 6 I UV is a voltage monitor that contributes to the PG output. The UV input has a 0.6 V threshold and is programmable via an external resistor divider. A UV voltage above 0.6V indicates a bus voltage that is above its minimum acceptable voltage. A low UV input does not effect the gate drive.
GND 7 PWR Device ground.
GATE 8 O Connect to the gate of the external MOSFET. Controls the MOSFET to emulate a low forward-voltage diode.
RSVD 9 PWR This pin must be connected to GND.
C 10 I Voltage sense input that connects to the simulated diode cathode. Connect to the MOSFET drain in the typical configuration.
A 11 I Voltage sense input that connects to the simulated diode anode. A also serves as the reference for the charge-pump bias supply on BYP. Connect to the MOSFET source in the typical configuration.
FLTR 12 I A capacitor connected from FLTR to A filters the input to the fast comparator. Filtering allows the TPS2410 to ignore spurious transients on the A and C inputs. This pin may be left open to achieve the fastest response time.
BYP 13 I/O Connect a storage capacitor from BYP to A to filter the gate drive supply voltage.
PG 14 O An open-drain Power Good indicator. PG is open if the UV input is above its threshold, the OV is below its threshold, and the internal UVLO is satisfied.
RMS Package
UQFN 14 Pin
Top View
TPS2410 TPS2411 RMS_qfn_pin_diagram.gif

Pin Functions, RMS

PIN I/O DESCRIPTION
NAME NO.
BYP 1 I/O Connect a storage capacitor from BYP to A to filter the gate drive supply voltage.
PG; 2 O An open-drain Power Good indicator. PG is open if the UV input is above its threshold, the OV is below its threshold, and the internal UVLO is satisfied.
VDD 3 PWR Input power for the gate drive charge pump and internal controls. VDD must be connected to a supply voltage ≥ 3 V.
RSET 4 I Connect a resistor to ground to program the turn-off threshold. Leaving RSET open results in a slightly positive V(A-C) turn-off threshold.
STAT 5 I/O STAT is a multifunction pin. A high output indicates that the MOSFET gate is being driven high. Overdriving STAT low while GATE is high shifts the fast-turnoff threshold negative. STAT has a weak pull-up to VDD.
FLTB 6 O Open drain fault output. Fault is active (low) for any of the following conditions:
  • Insufficient VDD
  • GATE should be high but is not.
  • The MOSFET should be ON but the forward voltage exceeds 0.4 V.
OV 7 I OV is a voltage monitor that contributes to the PG output, and also causes the MOSFET to turn off if it is above the 0.6-V threshold. OV is programmable via an external resistor divider. An OV voltage above 0.6 V indicates a bus voltage that is too high.
UV 8 I UV is a voltage monitor that contributes to the PG output. The UV input has a 0.6 V threshold and is programmable via an external resistor divider. A UV voltage above 0.6V indicates a bus voltage that is above its minimum acceptable voltage. A low UV input does not effect the gate drive.
GND 9 PWR Device ground.
GATE 10 O Connect to the gate of the external MOSFET. Controls the MOSFET to emulate a low forward-voltage diode.
RSVD 11 PWR This pin must be connected to GND.
C 12 I Voltage sense input that connects to the simulated diode cathode. Connect to the MOSFET drain in the typical configuration.
A 13 I Voltage sense input that connects to the simulated diode anode. A also serves as the reference for the charge-pump bias supply on BYP. Connect to the MOSFET source in the typical configuration.
FLTR 14 I A capacitor connected from FLTR to A filters the input to the fast comparator. Filtering allows the TPS2410 to ignore spurious transients on the A and C inputs. This pin may be left open to achieve the fastest response time.