SLVSAL2G January   2011  – November 2015 TPS24710 , TPS24711 , TPS24712 , TPS24713

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DETAILED PIN DESCRIPTIONS
        1. 8.3.1.1  EN
        2. 8.3.1.2  FLT
        3. 8.3.1.3  FLTb
        4. 8.3.1.4  GATE
        5. 8.3.1.5  GND
        6. 8.3.1.6  OUT
        7. 8.3.1.7  PG
        8. 8.3.1.8  PGb
        9. 8.3.1.9  PROG
        10. 8.3.1.10 SENSE
        11. 8.3.1.11 TIMER
        12. 8.3.1.12 VCC
    4. 8.4 Device Functional Modes
      1. 8.4.1 Board Plug In
      2. 8.4.2 Inrush Operation
      3. 8.4.3 Action of the Constant-Power Engine
      4. 8.4.4 Circuit Breaker and Fast Trip
      5. 8.4.5 Automatic Restart
      6. 8.4.6 PG, FLT, PGb, FLTb, and Timer Operations
      7. 8.4.7 Overtemperature Shutdown
      8. 8.4.8 Start-Up of Hot-Swap Circuit by VCC or EN
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power-Limited Start-Up
          1. 9.2.2.1.1 STEP 1. Choose RSENSE
          2. 9.2.2.1.2 STEP 2. Choose MOSFET M1
          3. 9.2.2.1.3 STEP 3. Choose Power-Limit Value, PLIM, and RPROG
          4. 9.2.2.1.4 STEP 4. Choose Output Voltage Rising Time, tON, CT
          5. 9.2.2.1.5 STEP 5. Calculate the Retry-Mode Duty Ratio
          6. 9.2.2.1.6 STEP 6. Select R1 and R2 for UV
          7. 9.2.2.1.7 STEP 7. Choose RGATE, R4, R5 and C1
        2. 9.2.2.2 Additional Design Considerations
          1. 9.2.2.2.1 Use of PG/PGb
          2. 9.2.2.2.2 Output Clamp Diode
          3. 9.2.2.2.3 Gate Clamp Diode
          4. 9.2.2.2.4 High-Gate-Capacitance Applications
          5. 9.2.2.2.5 Bypass Capacitors
          6. 9.2.2.2.6 Output Short-Circuit Measurements
          7. 9.2.2.2.7 Using Soft Start with TPS2471x
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Revision History

Changes from F Revision (February 2015) to G Revision

Changes from E Revision (November 2013) to F Revision

  • Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go
  • Changed the Input voltage range, PROG - MAX value in the Absolute Maximum Ratings table From: 0.3 To: 3.6 Go
  • Deleted External capacitance - GATE from the Recommended Operating ConditionsGo
  • Deleted text from the last paragraph in the GATE section "If used, any capacitor connecting GATE and GND should not exceed 1 μF and it should be connected in series with a resistor of no less than 1 kΩ."Go
  • Deleted section: Alternative Design Example: GATE Capacitor (dV/dt) Control in Inrush ModeGo
  • Deleted text from the High-Gate-Capacitance Applications section "When gate capacitor dV/dt control is used, ... then a Zener diode is not necessary."Go

Changes from D Revision (November 2013) to E Revision

Changes from C Revision (May 2011) to D Revision

  • Added Note 1 to the Supply Current Conditions statementGo
  • Added Note 1 to Fast-turnoff delay Go
  • Changed the Functional Block Diagram From: VCC = 6 V to VCC = 5.9 V at the Gate ComparatorGo
  • Changed text in the GATE section From: "Timer Activation Voltage (6 V for VVCC = 12 V)." To: "Timer Activation Voltage (5.9 V for VVCC = 12 V)."Go
  • Changed the first paragraph of the Inrush Operation sectionGo
  • Added text and new Equation 10Go
  • Changed text prior to Equation 12 From: "6 V (for VVCC = 12 V)" To: "5.9 V (for VVCC = 12 V)"Go
  • Changed the text following Equation 12Go
  • Changed text following Alternative Design Example: GATE Capacitor (dV/dt) Control in Inrush Mode From: "Set PLIM to a value greater than VVCC × ICHG" To: "Choose ICHG < PLIM / VVCC"Go
  • Changed Equation 15 From: – CISS To: – CRS (this equation deleted by Revision F)Go

Changes from B Revision (April 2011) to C Revision

  • Changed in PGb: from: 140V/340mV, to:170mV / 240mV Go
  • Changed in Equation 8: rDS(on) to RSENSEGo

Changes from A Revision (March 2011) to B Revision