SLVSCV6 Data sheet

SLVSCV6A January 2015 – February 2015 TPS24740 , TPS24741 , TPS24742

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RGE|24
- MPQF124G

サーマルパッド・メカニカル・データ

RGE|24
- QFND008AA

発注情報

8 Specifications

8.1 Absolute Maximum Ratings

Unless otherwise noted, these apply over recommended operating junction temperature: -40°C ≤ T_J ≤ 125°C. ⁽¹⁾

		MIN	MAX	UNIT
Input Voltage	CP, BGATE	–0.3	40	V
	VDD,SET, FSTP,SENM, OUTH, C, RVSNP, RVSNM, A, ENHS, ENOR, FLTb, PGHS, OV, STAT	–0.3	30	V
	CP, BGATE to A	–0.3	12	V
	HGATE to OUTH	–0.3	15	V
	SET to VDD	–0.3	0.3	V
	SENM, FSTP to VDD	–0.6	0.3	V
	A to C	–30	7	V
	RVSNM, to A, C, RVSNP RVSNP to A, C, RVSNM	–30	30	V
	TINR, TFLT, PLIM, IMON,	–0.3	3.6	V
	IMONBUF	–0.3	7	V
Sink Current	FLTb, PGHS, STAT		5	mA
Source Current	IMON, IMONBUF		5	mA
Storage temperature range, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

			VALUE	UNIT
V_(ESD)⁽¹⁾	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽²⁾	±1500	V
V_(ESD)⁽¹⁾	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽³⁾	±500	V

(1) Electrostatic discharge (ESD) measures device sensitivity and immunity to damage caused by assembly line electrostatic discharges into the device.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

These apply over recommended operating junction temperature: -40°C ≤ T_J ≤ 125°C.

		MIN	MAX	UNIT
Input voltage	VDD, SENM, SET⁽¹⁾, FSTP	2.5	18	V
	ENHS, ENOR, FLTb, PGHS, STAT, OUTH	0	18
	A, C, RVSNM, RVSNP; ⁽²⁾	0.7	18
Sink current	FLTb, PGHS, STAT	0	2	mA
Source current	IMON	0	1	mA
External resistance	PLIM	4.99	500	kΩ
	IMON	1	6	kΩ
	RVSNP	10	1000	Ω
	FSTP	10	4000	Ω
	SET	10	400	Ω
R_IMON / R_SET	w/o R_STBL⁽⁴⁾	10	70
R_IMON / R_SET	With appropriate R_STBL	3	10
External capacitor	CP, FSTP, RVSNP	1	1000	nF
	HGATE, BGATE ⁽³⁾	0	1	µF
	TINR, TFLT	1		nF
	IMON		30	pF
	IMONBUF		100	pF
Operating junction temperature, T_J		–40	125	°C

(1) Do not apply voltage to these pins.

(2) For the HS then ORing application these pins may be below the recommended minimum during start-up. The part is designed to function properly under these scenarios. However the part should not be used with a bus voltage below the recommended voltage.

(3) External capacitance tied to HGATE, BGATE should be in series with a resistor no less than 1kΩ.

(4) Refer to R_STBL Requirement for R_IMON / R_SET < 10 describe in section Select RSNS and VSNS,CL Setting.

8.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS24740, TPS24741, TPS24742	UNIT
THERMAL METRIC⁽¹⁾		RGE (24 PINS)	UNIT
R_θJA	Junction-to-ambient thermal resistance	34.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	38.4
R_θJB	Junction-to-board thermal resistance	12.9
ψ_JT	Junction-to-top characterization parameter	0.5
ψ_JB	Junction-to-board characterization parameter	12.9
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

Unless otherwise noted these limits apply to the following: -40°C ≤ T_J ≤ 125°C; 2.5V < V_VDD , V_OUTH < 18V; 0.7 V < V_A , V_C , V_RVSNM< 18 V; V_ENHS = V_ENOR = 2 V, V_OV = 0 V; V_BGATE, V_HGATE, V_PGHS, V_STAT, V_FLTb, and V_IMONBUF are floating; C_CP = 100 nF, C_INR = 1 nF, C_FLT = 1 nF, R_SET = 44.2 Ω, R_IMON = 2.98 kΩ, R_FSTP = 200 Ω, R_RV= 200 Ω, and R_PLIM = 52 kΩ.

PARAMETER		TEST CONDITION	MIN	TYP	MAX	UNIT
INPUT SUPPLY (VDD)
V_UVR	UVLO threshold, rising		2.2	2.32	2.45	V
V_UVhyst	UVLO hysteresis			0.1		V
I_QON	Supply current: I_VDD+I_A+I_C+ I_OUTH	Device on, V_ENHS = V_ENOR = 2V		4.2	6	mA
HOT SWAP FET ENABLE (ENHS)
V_ENHS	Threshold voltage, rising		1.3	1.35	1.4	V
V_ENHShyst	Hysteresis			50		mV
I_ENHS	Input Leakage Current	0 ≤ V_ENH_S ≤ 30V	–1		1	µA
BLOCKING (ORING) FET ENABLE (ENOR)
V_ENOR	Threshold voltage, rising		1.3	1.35	1.4	V
V_ENORhyst	Hysteresis			50		mV
I_ENOR	Input leakage current	0 V ≤ V_ENO_R ≤ 30V	–1	0	1	µA
OVER VOLTAGE (OV)
V_OVR	Threshold voltage, rising		1.3	1.35	1.4	mV
V_OVhyst	Hysteresis			50		mV
I_OV	Input leakage current	0 ≤ V_OV ≤ 30V	–1		1	µA
POWER LIMIT PROGRAMING (PLIM)
V_PLIM,BIAS	Bias voltage	Sourcing 10μA	0.66	0.675	0.69	V
V_IMON,PL	Regulated IMON voltage during power limit	R_PLIM = 52 kΩ; V_SENM-OUTH=12V;	114.75	135	155.25	mV
		R_PLIM = 105 kΩ; V_SENM-OUTH=12V;	56.95	67	77.05
		R_PLIM = 261 kΩ; V_SENM-OUTH=12V;	18.9	27	35.1
		R_PLIM = 105 kΩ; V_SENM-OUTH=2V;	341.7	402	462.3
		R_PLIM = 105 kΩ; V_SENM-OUTH=18V;	38.25	45	51.75
SLOW TRIP THRESHOLD (SET)
V_{OS_SET}	Input referred offset (V_SNS to V_IMON scaling)	R_SET = 44.2Ω; R_IMON=3kΩ to 1.2kΩ (corresponds to V_SNS,CL=10mV to 25mV)	–150		150	µV
V_{GE_SET}	Gain error (V_SNS to V_IMON scaling)⁽¹⁾		–0.4%		0.4%
FAST TRIP THRESHOLD PROGRAMMING (FSTP)
I_FSTP	FSTP input bias current	V_FSTP=12V	95	100	105	µA
V_FASTRIP	Fast trip threshold	R_FSTP = 200 Ω, V_SNS when V_HGATE ↓	18	20	22	mV
		R_FSTP = 1 kΩ, V_SNS when V_HGATE ↓	95	100	105
		R_FSTP = 4 kΩ, V_SNS when V_HGATE ↓	380	400	420
CURRENT MONITOR and CURRENT LIMIT PROGRAMING (IMON)
V_IMON,CL	Slow trip threshold at summing node	V_IMON↑, when I_TFLT starts sourcing	660	675	690	mV
CURRENT MONITOR (IMONBUF)
V_{OS_IMONBUF}	Buffer offset	V_IMON = 50mV to 675mV, Input referred	–3	0	3	mV
GAIN_IMONBUF	Buffer voltage gain	ΔV_IMONBUFF / ΔV_IMON	2.97	2.99	3.01	V
BW_IMONBUF	Buffer closed loop bandwidth	C_IMONBUF = 75pF		1		MHz
HOT SWAP GATE DRIVER (HGATE)
V_HGATE	HGATE output voltage	5 ≤ V_VDD ≤ 16V; measure V_HGATE-OUTH	12	13.6	15.5	V
V_HGATE	HGATE output voltage	2.5V <V_VDD < 5V; 16V <V_VDD < 20V measure V_HGATE-OUTH	7	7.95	15	V
V_HGATEmax	Clamp voltage	Inject 10μA into HGATE, measure V_{(HGATE – OUTH)}	12	13.9	15.5	V
I_HGATEsrc	Sourcing current	V_HGAT-OUT_H = 2V-10V	44	55	66	µA
I_{HGATEfastSink}	Sinking current for fast trip	V_HGATE-OUTH = 2V -15V; V_{(FSTP – SENM)} = 20mV	0.45	1	1.6	A
I_{HGATEsustSink}	Sustained sinking current	Sustained, V_HGATE-OUTH = 2V – 15V; V_ENHS = 0	30	44	60	mA
CURRENT SENSE NEGATIVE INPUT (SENM)
I_SENM	Input bias current	V_SENM = 12V		15	20	µA
INRUSH TIMER (TINR)
I_TINRsrc	Sourcing current	V_TINR= 0V, In power limit or current limit	8	10.25	12.5	µA
I_TINRsink	Sinking current	V_TINR = 2V, In regular operation	1.5	2	2.5	µA
V_TINRup	Upper threshold voltage	Raise V_TINR until HGATE starts sinking	1.3	1.35	1.4	V
V_TINRlr	Lower threshold voltage	Raise V_TINR to 2V. Reduce V_TINR until I_TINR is sourcing.	0.33	0.35	0.37	v
R_TINR	Bleed down resistance	V_VDD = 0V, V_TINR = 2V	70	104	130	kΩ
I_TINR-PD	Pulldown current	V_TINR = 2V, when V_ENHS = 0V	2	4.2	7	mA
V_IMON,_TINR	See ⁽²⁾	R_PLIM = 52kΩ, V_SENM = 12V, V_OUTH = 0 V. Raise IMON voltage and record IMON when TINR starts sourcing current	47.75	90	132.25	mV
V_IMON,_PL	See ⁽²⁾	R_PLIM = 52kΩ, V_SENM = 12V, V_OUTH = 0 V. Raise IMON voltage and record IMON when I_HGATE starts sinking current.	114.75	135	155.25	mV
ΔV_IMON,_TINR	See ⁽²⁾	R_PLIM = 52kΩ, V_SENM = 12V, V_OUTH = 0 V. ΔV_IMON,TINR = V_IMON,PL – V_IMON,TINR	23	45	67	mV
FAULT TIMER (TFLT)
I_TFLTsrc	Sourcing current	V_TFL_T = 0V, PGHS is high and in overcurrent	8	10.25	12.5	µA
I_TFLTsink	Sinking current	V_TFLT = 2V, Not in overcurrent	1.5	2	2.5	µA
V_TFLTup	Upper threshold voltage	Raise V_TFLT until HGATE starts sinking	1.3	1.35	1.4	V
R_TFLT	Bleed down resistance	V_VDD = 0V, V_TFLT = 2V	70	104	130	kΩ
I_TFLT-PD	Pulldown current	V_TFLT = 2V, when V_ENHS = 0V	2	5.6	7	mA
HOT SWAP OUTPUT (OUTH)
I_{OUTH, BIAS}	Input bias current	V_OUTH= 12V		30	70	µA
CHARGE PUMP FOR BGATE (CP)
I_CP	CP Equivalent charging resistance	V_A = 12 V , 1mA CP current	5	8.7	12.5	kΩ
V_CP	CP Output voltage	Max(V_A, V_C, V_VDD) > 6 V, Measure V_CP-A	9	10	11	V
		6V > Max(V_A, V_C, V_VDD) > 4V, Measure V_CP-A	5	5.9	11
		Max(V_A, V_C, V_VDD) = 2.5 V, Measure V_CP-A	8	9.8	11
BLOCKING/ORING GATE DRIVER (BGATE)
I_{BGATE_CHRG}	BGATE Pull up current	V_AC= 20mV, pulse		30		mA
I_{BGATE_CHRG}	BGATE Pull up current	V_AC = 20mV, sustained	0.2	0.3	0.4	mA
I_{BGATEsustSink}	BGATE Sinking current	Fast turnoff, V_BGATE-A = 7V	0.4	0.9	1.4	A
I_{BGATEsustSink}	BGATE Sinking current	Sustained, V_BGATE-A = 2V to 11V	19	35	65	mA
BLOCKING/ORing ANODE (A)
I_A	Input current⁽³⁾	2.5 V ≤ V_A≤ 18V			3	mA
V_{A_UVLO}	Undervoltage lockout	V_A increasing and V_VDD=V_C=0.7V	1.85	1.93	2.05	V
V_{A_UVLO_hyst}	Undervoltage lockout hysteresis			0.1		V
BLOCKING/ORing CATHODE (C)
I_C	Input current⁽³⁾	2.5 V ≤ V_C ≤ 18V			3	mA
V_{C_UVLO}	Undervoltage lockout	V_C increasing and V_DD=V_A=0.7V	1.85	1.93	2.05	V
V_{C_UVHyst}	Hysteresis			100		mV
V_FWDTH	Forward turn-on voltage	Measure V_AC when V_{BGATE ↑}	7.5	10	12.5	mV
POSITIVE INPUT OF REVERSE VOLTAGE COMPARATOR (RVSNP)
I_RVSNP	RVSNP Input bias current	V_RVSNP = 12V, sinking current; 0.7V < V_A, V_RVSNM < 20V	93	99	105	µA
V_RVTRIP1	Reverse Comparator Offset	R_RV=10Ω, Measure V_RVSNP-RVSNM, when BGATE↓	-1	0	1	mV
NEGATIVE INPUT OF REVERSE VOLTAGE COMPARATOR (RVSNM)
I_RVSNM	Leakage current		–2		2	µA
FAULT INDICATOR (FLTb)
V_{OL_FLTb}	Output low voltage	Sinking 2 mA		0.11	0.25	V
I_FLTb	Input Leakage Current	V_FLT_b = 0V, 30V	–1	0	1	µA
V_{HSFLT_IMON}	V_IMON threshold to detect Hot Swap FET short	V_ENHS= 0V, Measured V_IMON ↑ to GND when FLTb ↓	88	101	115	mV
V_{HSFL_hyst}	Hysteresis			25		mV
V_{BFET, OPEN, FLT}	A-C threshold to detect OPEN Blocking/ORing FET fault	V_ENOR=3V, Measure V_A-C to FLTb↓, V_CP-A > 7V	350	410	490	mV
V_{CP_FLT}	CP fault threshold	Measure V_CP-A ↓ when FLTb↓, 4V ≤ V_VDD < 18V	5	5.5	6	V
V_{CP_FLT}	CP fault threshold	Measure V_CP-A ↓ when FLTb↓, 2.5V < V_VDD < 4V	3.3	3.75	4.2	V
V_{CP, FLT, hyst}	Hysteresis	4V ≤ V_VDD < 18V		1.5		V
V_{CP, FLT, hyst}	Hysteresis	2.5V < V_VDD < 4V		1.1		V
HOT SWAP POWER GOOD OUTPUT (PGHS)
V_PGHSth	PGHS Threshold	Measure V_SENM-OUTH ↓ when PGHS↑	170	270	375	mV
V_PGHShyst	PGHS hysteresis	V_SENM-OUTH ↑		80		mV
V_{OL_PGHS}	PGHS Output low voltage	Sinking 2mA		0.11	0.25	V
I_PGHS	PHGS Input leakage current	V_PGHS=0V to 30V	–1	0	1	µA
STATUS INDICATOR (STAT)
V_STATon	Status ON threshold	4V ≤ V_VDD < 20V , Measure V_{BGATE – A} ↑, when STAT↑	5	6	7	V
V_STATon	Status ON threshold	2.5V < V_VDD < 4V , Measure V_{BGATE – A} ↑, when STAT↑	3.6	4	4.4	V
V_STAToff	Status OFF threshold	4V < V_VDD < 20V , Measure V_{BGATE – A} ↓, when STAT↓	4	5	6	V
V_STAToff	Status OFF threshold	2.5V <V_VDD < 4V , Measure V_{BGATE – A} ↑, when STAT↑	2	2.7	3.4	V
V_STAT,LOWoff	STAT Output low voltage	Sinking 2 mA		0.11	0.25	V
I_STAT,LEAK	STAT Input leakage current	V_STAT = 0 V, 30 V	–1	0	1	µA
THERMAL SHUTDOWN (OTSD)
T_OTSD	Thermal shutdown threshold	Temperature rising		140		°C
T_OTSD,HYST	Hysteresis			10		°C

(1) Specified by characterization, not production tested.

(2) For more detail on the definition and usage of these parameters refer to section Using SoftStart – IHGATE and TINR Considerations.

(3) The TPS2474x is set up to be powered from A, C, or VDD depending on the biasing condition. See Internal Power ORing of TPS24740 To obtain the total current draw from A, C, VDD, and OUTH refer to the spec for Input Supply (VDD)..

8.6 Timing Requirements

PARAMETER		TEST CONDITION	MIN	TYP	MAX	UNIT
INPUT SUPPLY (VDD)
DEGL_UVLO	UVLO deglitch	Both rising and falling		14		µs
HOT SWAP FET ENABLE (ENHS)
DEGL_ENHS	Deglitch time	Both rising and falling	2.2	3.8	5.5	µs
BLOCKING (ORING) FET ENABLE (ENOR)
DEGL_ENOR	Deglitch time	Both rising and falling	1.7	3.5	5	µs
OVER VOLTAGE (OV)
DEGL_OV	Deglitch time	Both rising and falling	2.2	3.9	5.7	µs
HOT SWAP GATE DRIVER (HGATE)
t_HGATEdly	Turn on delay	CP ↑ to I_HGATE sourcing		1.9		ms
FAST TRIP (FSTP)
t_FastOffDly	Fast turn-off delay	V_{(FSTP – SENM)} : –5mV to 5mV, C_HGAT_E = 0 pF		600		ns
t_FastOffDly	Fast turn-off delay	V_{(FSTP – SENM)} : -20mV to 20mV C_HGATE = 0 pF		300		ns
t_FastOffDur	Strong pull down current duration		53	63	73	µs
INRUSH TIMER (TINR)
N_RETRY	Number of TINR cycles before retry	TPS24741 only		64
RETRY_DUTY	Retry duty cycle	T_INR not connected to T_FLT		0.35%
RETRY_DUTY	Retry duty cycle	T_INR connected to T_FLT		0.7%
BLOCKING/OR_ING GATE DRIVER (BGATE)
t_FastOffDur	Strong pull down current duration		10	15	20	µs
t_FastOnDur	Strong pull up current duration		10	20	30	µs
POSITIVE INPUT OF REVERSE VOLTAGE COMPARATOR (RVSNP)
t_FastOffDly	Turn-off delay	V_{(RVSNP –RVSNM}) = –5mV → 5mV, C_BGATE = 0 pF		340		ns
t_FastOffDly	Turn-off delay	V_{(RVSNP –RVSNM)} = –20mV → +20mV, C_BGATE = 0 pF		150		ns
FAULT INDICATOR (FLTb)
t_{FLT_degl}	HS / OR Fault Deglitch	Both HS and ORing faults	2.2	3.9	5.3	ms
t_{FLT_CP_degl}	CP fault deglitch		26.5	32	37.2	ms
HOT SWAP POWER GOOD OUTPUT (PGHS)
t_PGHSdegl	PGHS deglitch time	Rising	0.7	1	1.3	ms
t_PGHSdegl	PGHS deglitch time	Falling	7	8	9	ms
STATUS INDICATOR (STAT)
t_STATdegl	STAT Delay (deglitch) time	Rising or falling edge	0.4	0.95	1.5	ms

8.7 Typical Characteristics

Unless otherwise noted these limits apply to the following: V_VDD = V_A = V_C = V_RVSNM= V_OUTH = 12 V; V_ENHS = V_ENOR = 2 V, V_OV = 0 V; V_BGATE, V_HGATE, V_PGHS, V_STAT, V_FLTb, and V_IMONBUF are floating; C_CP = 100 nF, C_INR = 1 nF, C_FLT = 1 nF, R_SET = 44.2 Ω, R_IMON = 2.98 kΩ, R_FSTP = 200 Ω, R_RV= 200 Ω, and R_PLIM = 52 kΩ.