JAJSGL9C October   2013  – December 2018 TPS24750 , TPS24751

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション回路図 (12V、10A)
      2.      過渡出力短絡応答
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Descriptions
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  DRAIN
      2. 9.3.2  EN
      3. 9.3.3  FLTb
      4. 9.3.4  GATE
      5. 9.3.5  GND
      6. 9.3.6  IMON
      7. 9.3.7  OUT
      8. 9.3.8  OV
      9. 9.3.9  PGb
      10. 9.3.10 PROG
      11. 9.3.11 SENSE
      12. 9.3.12 TIMER
      13. 9.3.13 VCC
    4. 9.4 Device Functional Modes
      1. 9.4.1 Board Plug-In
      2. 9.4.2 Inrush Operation
      3. 9.4.3 Action of the Constant-Power Engine
      4. 9.4.4 Circuit Breaker and Fast Trip
      5. 9.4.5 Automatic Restart
      6. 9.4.6 Start-Up with Short on Output
      7. 9.4.7 PGb, FLTb, and Timer Operations
        1. 9.4.7.1 Overtemperature Shutdown
        2. 9.4.7.2 Start-Up of Hot-Swap Circuit by VCC or EN
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power-Limited Start-Up
          1. 10.2.2.1.1 STEP 1. Choose RSENSE, RSET, and RIMON
          2. 10.2.2.1.2 STEP 2. Choose Power-Limit Value, PLIM, and RPROG
          3. 10.2.2.1.3 STEP 3. Choose Output Voltage Rising Time, tON, and Timing Capacitor CT
          4. 10.2.2.1.4 STEP 4. Calculate the Retry-Mode Duty Ratio
          5. 10.2.2.1.5 STEP 5. Select R1, R2, and R3 for UV and OV
          6. 10.2.2.1.6 STEP 6. Choose R4, R5, and C1
        2. 10.2.2.2 Alternative Design Example: Gate Capacitor (dv/dt) Control in Inrush Mode
        3. 10.2.2.3 Additional Design Considerations
          1. 10.2.2.3.1 Use of PGb
          2. 10.2.2.3.2 Output Clamp Diode
          3. 10.2.2.3.3 Gate Clamp Diode
          4. 10.2.2.3.4 Bypass Capacitors
          5. 10.2.2.3.5 Output Short-Circuit Measurements
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
    1. 11.1 Transient Thermal Impedance
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Export Control Notice
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

–40°C ≤ TJ ≤ +125°C, VCC = 12 V, VEN = 3 V, RSET = 191 Ω, RIMON = 5 kΩ, and RPROG = 50 kΩ to GND. All voltages referenced to GND, unless otherwise noted.
PARAMETER CONDITIONS MIN NOM MAX UNIT
VCC
UVLO threshold, rising 2.20 2.32 2.45 V
UVLO threshold, falling 2.10 2.22 2.35 V
UVLO hysteresis(1) 0.1 V
Supply current Enabled ― IOUT + IVCC + ISENSE 0.5 1 1.4 mA
Disabled(1) ― EN = 0 V, IOUT + IVCC + ISENSE 0.45 mA
OUT
RON On-resistance 1 A ≤ IOUT ≤ 10 A at TJ = 25°C 3 3.5 mΩ
1 A ≤ IOUT ≤ 10 A at TJ = 125°C 5 6 mΩ
Input bias current VOUT = 12 V 10 16 30 µA
Diode forward voltage VEN = 0 V, IOUT = –100 mA, VOUT > VSENSE 0.8 1 V
Leakage current - DRAIN to OUT VEN = 0 V, VOUT = 0 V, VDRAIN = 18 V at 25°C 0 1 µA
VEN = 0 V, VOUT = 0 V, VDRAIN = 18 V at 125°C 2 5 µA
Ciss Input capacitance VGS = 0 V, VDRAIN-OUT = 15 V, f = 1 MHz 2710 3250 pF
Coss Output capacitance 635 762 pF
Crss Reverse transfer capacitance 48 60 pF
Qg Gate charge total (4.5 V) VDRAIN-OUT = 15 V, IOUT = 20 A 17.5 21.5 nC
Qg(th) Gate charge at Vth 4.1 nC
EN
Threshold voltage, falling 1.2 1.3 1.4 V
Hysteresis(1) 50 mV
Input leakage current 0 V ≤ VEN ≤ 30 V –1 0 1 µA
Turnoff time EN ↓ to VGATE < 1 V 3 8 25 µs
Deglitch time EN ↑ 8 14 21 µs
Disable delay EN ↓ to GATE ↓, CGATE = 0, tpff50–90, See Figure 28 0.1 0.4 1.8 µs
Turnon delay COUT = 2.2 uF, VEN ↑ to VOUT ↑, VEN: 0 V to 3 V, VOUT : 90% VCC 800 µs
OV
Threshold voltage, rising 1.25 1.35 1.45 V
Hysteresis(1) 60 mV
Input leakage current 0 V ≤ VOV ≤ 30 V –1 0 1 µA
Deglitch time OV rising 0.5 1.2 1.5 µs
FLTb
Output low voltage Sinking 2 mA 0.11 0.25 V
Input leakage current VFLTb = 0 V, 30 V –1 0 1 µA
PGb
Threshold V(SENSE – OUT) rising, PGb going high 140 220 340 mV
Hysteresis(1) Measured V(SENSE – OUT) falling, PGb going low 70 mV
Output low voltage Sinking 2 mA 0.11 0.25 V
Input leakage current VPGb = 0 V, 30 V –1 0 1 µA
Delay (deglitch) time Rising or falling edge 2 3.4 6 ms
PROG
Bias voltage Sourcing 10 µA 0.65 0.675 0.7 V
Input leakage current VPROG = 1.5 V –0.2 0 0.2 µA
TIMER
Sourcing current VTIMER = 0 V 8 10 12 µA
Sinking current VTIMER = 2 V 8 10 12 µA
VEN = 0 V, VTIMER = 2 V 2 4.5 7 mA
Upper threshold voltage 1.3 1.35 1.4 V
Lower threshold voltage 0.33 0.35 0.37 V
Timer activation voltage Raise GATE until ITIMER sinking, measure V(GATE – VCC), VVCC = 12 V 5 5.8 7 V
Retry duty cycle During over current and short circuit conditions (TPS24751 only) 4%
IMON
Circuit breaker threshold 650 675 696 mV
Input referred offset of servo amplifier At TJ = 25°C –1 0 1 mV
TJ from –40°C to +125°C –1.5 0 1.5 mV
SET
Input referred offset of servo amplifier Measure SET to SENSE –1.5 0 1.5 mV
GATE
Output voltage VOUT = 12 V 23.5 25.7 28 V
Clamp voltage Inject 10 µA into GATE, measure V(GATE – VCC) 12 13.9 15.5 V
Sourcing current VGATE = 12 V 20 30 40 µA
Sinking current Fast turnoff, VGATE = 14 V 0.4 1 1.4 A
Sustained, VGATE = 4 V to 23 V 6 11 20 mA
In inrush current limit, VGATE = 4 V to 23 V 20 30 40 µA
Pulldown resistance Thermal shutdown or VEN = 0 V 14 20 26 kΩ
Fast turnoff duration 8 13 18 µs
Turnon delay VVCC rising to GATE sourcing, tprr50-50, See Figure 29 100 375 µs
SENSE
Input bias current VSENSE = 12 V, sinking current 30 40 µA
Current limit threshold VOUT = 12 V 22.5 25 27.5 mV
Power limit threshold VDRAIN–OUT = 8 V, RPROG = 100 kΩ 4 mV
VDRAIN–OUT = 8 V, RPROG = 50 kΩ 6.6 8 9.6
VDRAIN–OUT = 5.37 V, RPROG = 50 kΩ 10 12 14
VDRAIN–OUT = 10.3 V, RPROG = 25 kΩ 10 12.5 15
Fast-trip threshold 52 60 68 mV
Fast-turnoff delay(1) V(VCC – SENSE) = 80 mV, CGATE = 0 pF, tprf50–50, See Figure 30 200 ns
OTSD
Threshold, rising Temperature referenced to PAD1 of the device. See(2) 130 140 °C
Hysteresis(1) 10 °C
(1) These parameters are provided for reference only and do not constitute part of TI’s published device specifications for purposes of TI’s product warranty.
(2) The temperature difference between PAD1 and PAD2 must be minimized. See the SOA curve Figure 27 and Power-Limited Start-Up section for temperature limited design.