JAJSGL9C October   2013  – December 2018 TPS24750 , TPS24751

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション回路図 (12V、10A)
      2.      過渡出力短絡応答
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Descriptions
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  DRAIN
      2. 9.3.2  EN
      3. 9.3.3  FLTb
      4. 9.3.4  GATE
      5. 9.3.5  GND
      6. 9.3.6  IMON
      7. 9.3.7  OUT
      8. 9.3.8  OV
      9. 9.3.9  PGb
      10. 9.3.10 PROG
      11. 9.3.11 SENSE
      12. 9.3.12 TIMER
      13. 9.3.13 VCC
    4. 9.4 Device Functional Modes
      1. 9.4.1 Board Plug-In
      2. 9.4.2 Inrush Operation
      3. 9.4.3 Action of the Constant-Power Engine
      4. 9.4.4 Circuit Breaker and Fast Trip
      5. 9.4.5 Automatic Restart
      6. 9.4.6 Start-Up with Short on Output
      7. 9.4.7 PGb, FLTb, and Timer Operations
        1. 9.4.7.1 Overtemperature Shutdown
        2. 9.4.7.2 Start-Up of Hot-Swap Circuit by VCC or EN
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power-Limited Start-Up
          1. 10.2.2.1.1 STEP 1. Choose RSENSE, RSET, and RIMON
          2. 10.2.2.1.2 STEP 2. Choose Power-Limit Value, PLIM, and RPROG
          3. 10.2.2.1.3 STEP 3. Choose Output Voltage Rising Time, tON, and Timing Capacitor CT
          4. 10.2.2.1.4 STEP 4. Calculate the Retry-Mode Duty Ratio
          5. 10.2.2.1.5 STEP 5. Select R1, R2, and R3 for UV and OV
          6. 10.2.2.1.6 STEP 6. Choose R4, R5, and C1
        2. 10.2.2.2 Alternative Design Example: Gate Capacitor (dv/dt) Control in Inrush Mode
        3. 10.2.2.3 Additional Design Considerations
          1. 10.2.2.3.1 Use of PGb
          2. 10.2.2.3.2 Output Clamp Diode
          3. 10.2.2.3.3 Gate Clamp Diode
          4. 10.2.2.3.4 Bypass Capacitors
          5. 10.2.2.3.5 Output Short-Circuit Measurements
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
    1. 11.1 Transient Thermal Impedance
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Export Control Notice
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.4.7.2 Start-Up of Hot-Swap Circuit by VCC or EN

The connection and disconnection between a load and the input power bus are controlled by turning on and turning off the internal FET.

The TPS2475x has two ways to turnon the internal FET:

  • Increasing VVCC above UVLO upper threshold while EN is already higher than its upper threshold sources current to the gate of internal FET. After an inrush period, the TPS2475x fully turns on internal FET.
  • Increasing EN above its upper threshold while VVCC is already higher than the UVLO upper threshold sources current to the gate of internal FET. After an inrush period, the TPS2475x fully turns on internal FET.

The EN pin can be used to start up the TPS2475x at a selected input voltage VVCC.

To isolate the load from the input power bus, the internal FET can be disabled by any of the following conditions: UVLO, EN, load current above the current-limit threshold, hard short at load, OV, or OTSD. Three separate mechanisms disable the internal FET by pulling down the GATE as described below:

  1. GATE is pulled down by an 11-mA current source when any of the following occurs.
    • The fault timer expires during an overload current fault (VIMON > 675 mV).
    • VEN is below its falling threshold.
    • VVCC drops below the UVLO threshold.
    • VOV is above its rising threshold.
  2. GATE is pulled down by a 1-A current source for 13.5 μs when a hard output short circuit occurs and V(VCC – SENSE) is greater than 60 mV, that is, the fast-trip shutdown threshold. After fast-trip shutdown is complete, an 11-mA sustaining current ensures that the internal FET remains off.
  3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising threshold.