JAJSGL9C October   2013  – December 2018 TPS24750 , TPS24751

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション回路図 (12V、10A)
      2.      過渡出力短絡応答
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Descriptions
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  DRAIN
      2. 9.3.2  EN
      3. 9.3.3  FLTb
      4. 9.3.4  GATE
      5. 9.3.5  GND
      6. 9.3.6  IMON
      7. 9.3.7  OUT
      8. 9.3.8  OV
      9. 9.3.9  PGb
      10. 9.3.10 PROG
      11. 9.3.11 SENSE
      12. 9.3.12 TIMER
      13. 9.3.13 VCC
    4. 9.4 Device Functional Modes
      1. 9.4.1 Board Plug-In
      2. 9.4.2 Inrush Operation
      3. 9.4.3 Action of the Constant-Power Engine
      4. 9.4.4 Circuit Breaker and Fast Trip
      5. 9.4.5 Automatic Restart
      6. 9.4.6 Start-Up with Short on Output
      7. 9.4.7 PGb, FLTb, and Timer Operations
        1. 9.4.7.1 Overtemperature Shutdown
        2. 9.4.7.2 Start-Up of Hot-Swap Circuit by VCC or EN
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power-Limited Start-Up
          1. 10.2.2.1.1 STEP 1. Choose RSENSE, RSET, and RIMON
          2. 10.2.2.1.2 STEP 2. Choose Power-Limit Value, PLIM, and RPROG
          3. 10.2.2.1.3 STEP 3. Choose Output Voltage Rising Time, tON, and Timing Capacitor CT
          4. 10.2.2.1.4 STEP 4. Calculate the Retry-Mode Duty Ratio
          5. 10.2.2.1.5 STEP 5. Select R1, R2, and R3 for UV and OV
          6. 10.2.2.1.6 STEP 6. Choose R4, R5, and C1
        2. 10.2.2.2 Alternative Design Example: Gate Capacitor (dv/dt) Control in Inrush Mode
        3. 10.2.2.3 Additional Design Considerations
          1. 10.2.2.3.1 Use of PGb
          2. 10.2.2.3.2 Output Clamp Diode
          3. 10.2.2.3.3 Gate Clamp Diode
          4. 10.2.2.3.4 Bypass Capacitors
          5. 10.2.2.3.5 Output Short-Circuit Measurements
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
    1. 11.1 Transient Thermal Impedance
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Export Control Notice
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2.2.1.3 STEP 3. Choose Output Voltage Rising Time, tON, and Timing Capacitor CT

The maximum output voltage rise time, tON, set by timer capacitor CT must suffice to fully charge the load capacitance COUT without triggering the fault circuitry. Equation 9 defines tON for two possible inrush cases. Assuming that only the load capacitance draws current during startup,

Equation 9. TPS24750 TPS24751 EQ_tON_slvsc87.gif

The next step is to determine the minimum fault-timer period. In Equation 9, the output rise time is tON. This is the amount of time it takes to charge the output capacitor up to the final output voltage. However, the fault timer uses the difference between the input voltage and the gate voltage to determine if the TPS2475x is still in inrush limit. The fault timer continues to run until VGS rises 5.8 V (for VVCC = 12 V) above the input voltage. Some additional time must be added to the charge time to account for this additional gate voltage rise. The minimum fault time can be calculated using Equation 10.

Equation 10. TPS24750 TPS24751 EQ_tFLT_slvsc87.gif

where QGINT is the Gate charge of the internal FET to reach the 5.8 V gate voltage (see Figure 25), QGBLK is the Gate charge of blocking FET (for this design, it is considered that CSD17501Q5A SLPS303 blocking FET is used, take this as '0' if blocking FET is not used) and IGATE is the minimum gate sourcing current of the TPS2475x, or 20 μA. Overall, Equation 10 leads to a minimum fault time of 4.184 ms. Considering the tolerances of COUT, CT, ILIM , ITIMER and PLIM, the fault timer must be set to a value ≥ 1.4 times of tFLT obtained, to avoid turning off during start-up, but need to be lower than any maximum fault time limit determined by the device SOA curve (see Figure 27).

For this example, we select 6.3 ms (1.5 x TFLT) to allow for variation of system parameters such as temperature, load, component tolerance, and input voltage. As per SOA curve (TA = 25oC), for approximately 6.5 ms, the power handled by the device is approximately 70 W at 12 V (value obtained from extrapolation). This need to be scaled (derated) by a factor of (150 –TJDCMAX))/(150 – TA), where TJDCMAX is the maximum steady state junction temperature (TJDMAX = TA(MAX) + ILIM2 × R(DS)ON × RθJA). The scaled power is approximately 34 W. So the power limit of 21 W considered has safe margin of 38% over the derated SOA. This can be depicted through the Figure 42. Also, from Figure 42, from the blue dotted line shown, it can be analyzed that the device at TA = 25oC, can tolerate 12 V and 10 A for approximately time 1 ms and can take power of 21 W for duration of approximately 70 to 75 ms.

The timing capacitor is calculated in Equation 11 as 46.67 nF. Selecting the next-highest standard value, 47 nF, yields a 6.35 ms fault time.

Equation 11. TPS24750 TPS24751 EQ_Ct_2_slvsc87.gif
TPS24750 TPS24751 G009_slvsc87.gifFigure 42. Design Example SOA