SLVSCZ3 March   2015 TPS24770 , TPS24771 , TPS24772

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Enable and Over-voltage Protection
      2. 9.3.2 Current Limit and Power Limit during Start-up
      3. 9.3.3 Two Level Protection During Regular Operation
      4. 9.3.4 Dual Timer (TFLT and TINR)
      5. 9.3.5 3 Options for Response to a Fast Trip
      6. 9.3.6 Using Soft Start - IHGATE and TINR Considerations
      7. 9.3.7 Analog Current Monitor
      8. 9.3.8 Power Good Flag
      9. 9.3.9 Fault Reporting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Hot Swap Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 12 V, 100 A, 5,500 µF Analog Hot Swap Design
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design Procedure
        1. 10.2.3.1  Select RSNS and VSNS,CL Setting
        2. 10.2.3.2  Selecting the Fast Trip Threshold and Filtering
        3. 10.2.3.3  Selecting the Hot Swap FET(s)
        4. 10.2.3.4  Select Power Limit
        5. 10.2.3.5  Set Fault Timer
        6. 10.2.3.6  Check MOSFET SOA
        7. 10.2.3.7  Choose Under Voltage and Over Voltage Settings
        8. 10.2.3.8  Selecting C1 and COUT
        9. 10.2.3.9  Adding CENHS
        10. 10.2.3.10 Selecting D1 and D2
        11. 10.2.3.11 Checking Stability
        12. 10.2.3.12 Compute Tolerances
      4. 10.2.4 Application Curves
      5. 10.2.5 240 VA Application Using CSD16415Q5B
        1. 10.2.5.1 Design Requirements
        2. 10.2.5.2 Theory of Operations
        3. 10.2.5.3 Design Procedure
          1. 10.2.5.3.1 Select VSNS,CL, RSNS, and RSET Setting
            1. 10.2.5.3.1.1 Select RPOW and RIMON
            2. 10.2.5.3.1.2 Selecting the Hot Swap FET(s)
            3. 10.2.5.3.1.3 Keeping MOSFET within SOA During Normal Start-up
            4. 10.2.5.3.1.4 Choose Fault Timer
            5. 10.2.5.3.1.5 Choose Under Voltage and Over Voltage Settings
            6. 10.2.5.3.1.6 Selecting CIN and COUT
            7. 10.2.5.3.1.7 Selecting D1 and D2
            8. 10.2.5.3.1.8 Adding CENHS
            9. 10.2.5.3.1.9 Stability Considerations
        4. 10.2.5.4 Application Curves
      6. 10.2.6 240 VA Application Using CSD17573Q5B
        1. 10.2.6.1 Design Requirements
          1. 10.2.6.1.1 Choosing C1, COUT, CFLT, CENHS, D1, D2, RSET, RPOW, RIMON, RSNS, CDVDT, RPLIM, and UV/OV Thresholds
          2. 10.2.6.1.2 Selecting the Hot Swap FET(s)
          3. 10.2.6.1.3 Keeping the MOSFET within SOA
        2. 10.2.6.2 Q2 Selection
        3. 10.2.6.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

12 Layout

12.1 Layout Guidelines

When doing the layout of the TPS2477x the following are considered best practice.

  • Ensure proper Kelvin Sense of RSNS.
  • Keep the filtering capacitor CFSTP as close to the IC as possible.
  • Place a Shottky diode and a ceramic bypass capacitor close to the source of the Hot Swap MOSFET
  • Do not connect VDD to the Kelvin Sense trace for SET and FSTP
  • Note that special care must be taken when placing the bypass capacitor for the VDD pin. During Hot Shorts, there is a very large dv/dt on input voltage during the MOSFET turn off. If the bypass capacitor is placed right next to the pin and the trace from RSNS to the pin is long, an LC filter is formed. As a result a large differential voltage can develop between VDD and SENM if there is a large transient on Vin. This could result in a violation of the abs max rating from VDD to SENM. To avoid this, place the bypass capacitor close to RSNS instead of the VDD pin.
    • TPS24770 TPS24771 TPS24772 LayoutDonts_slvscz3.gifFigure 51. Layout Don't
  • When using parallel resistors the layout becomes even more critical. Due to PCB parasitics, the current through each RSNS may be different, which results in different sense voltages across the two resistors. It’s important to average these in order to get a proper current measurement. This can be accomplished by forming a resistor divider with the traces. As long as Dis1 = Dis2, the final VSNS will be an average of the drop across the two resistors.
    • TPS24770 TPS24771 TPS24772 2RSNS.gifFigure 52. Sense Layout with 2 RSNS

12.2 Layout Example

TPS24770 TPS24771 TPS24772 Layout.gif