11.1 Layout Guidelines

Layout is an important design step due to the high switching frequency of the boost converter. Careful attention must be applied to the PCB layout to ensure proper function of the device and to obtain the specified performance. Potential issues resulting from poor layout techniques include wider line and load regulation tolerances, EMI noise issues, stability problems, and USB current-limit shifts. It is critical to provide a low-impedance ground path that minimizes parasitic inductance. Wide and short traces should be used in the high-current paths, and components should be placed as close to the device as possible. Grounding is an important part of the layout. The device has a PGND and a GND pin. The GND pin is the quiet analog ground of the device and should have its own separate ground pour; connect the quiet signals to GND including the RILIM1/2 resistors and any input decoupling capacitors to the GND pour. It is important that the RILIM1/2 resistors be tied to a quiet ground to avoid unwanted shifts in the current-limit threshold. The PGND pin is the high-current power-stage ground; the ground pours of the output (AUX) and bulk input capacitors should be tied to PGND. PGND and GND should to be tied together in one location at the IC thermal pad, creating a star-point ground.

The output filter of the boost converter is also critical for layout. The inductor and AUX capacitors should be placed to minimize the area of current loop through AUX–PGND–SW.The layout for the TPS2505EVM evaluation board is shown in Figure 16 and should be followed as closely as possible for best performance.

11.2 Layout Example

Figure 16. Layout Recommendation for TPS2505 Application – 4 Layer Board