JAJSBO7A February   2012  – October 2016 TPS2543

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Electrical Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics, High-Bandwidth Switch
    7. 6.7 Electrical Characteristics, Charging Controller
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Standard Downstream Port (SDP) USB 2.0/USB 3.0
      2. 8.3.2  Charging Downstream Port (CDP)
      3. 8.3.3  Dedicated Charging Port (DCP)
        1. 8.3.3.1 DCP BC1.2 and YD/T 1591-2009
        2. 8.3.3.2 DCP Divider Charging Scheme
      4. 8.3.4  Wake on USB Feature (Mouse/Keyboard Wake Feature)
        1. 8.3.4.1 USB 2.0 Background Information
        2. 8.3.4.2 Wake On USB
        3. 8.3.4.3 USB Slow-Speed Device Recognition and Operation
      5. 8.3.5  Load Detect
      6. 8.3.6  Power Wake
        1. 8.3.6.1 Implementing Power Wake in Notebook System
      7. 8.3.7  Port Power Management (PPM)
        1. 8.3.7.1 Benefits of PPM
        2. 8.3.7.2 PPM Details
        3. 8.3.7.3 Implementing PPM in a System with Two Charging Ports
      8. 8.3.8  Over-Current Protection
      9. 8.3.9  FAULT Response
      10. 8.3.10 Undervoltage Lockout (UVLO)
      11. 8.3.11 Thermal Sense
    4. 8.4 Device Functional Modes
      1. 8.4.1 DCP Auto Mode
      2. 8.4.2 DCP Forced Shorted / DCP Forced Divider1
      3. 8.4.3 High-Bandwidth Data Line Switch
      4. 8.4.4 Device Truth Table (TT)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Discharge
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Current-Limit Settings
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

Refer to the simplified device state diagram in Figure 38. Power-on-reset (POR) holds device in initial state while output is held in discharge mode. Any POR event will take the device back to initial state. After POR clears, device goes to the next state depending on the CTL lines as shown in Figure 38.

TPS2543 Fig33_Charging_States_SLVSBW2.gif Figure 38. TPS2543 Charging States

9.1.1 Output Discharge

To allow a charging port to renegotiate current with a portable device, TPS2543 uses the OUT discharge function. It proceeds by turning off the power switch while discharging OUT, then turning back on the power switch to reassert the OUT voltage. This discharge function is automatically applied as shown in device state diagram.

9.2 Typical Application

TPS2543 typ_app_FP_SLVSBA6.gif Figure 39. Typical Application Schematic USB Port Charging

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 4.

Table 4. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage, V(IN) 5 V
Output voltage, V(DC) 5 V
Maximum continuous output current, I(OUT) 2.5 A
Current limit, I(LIM_LO) at RILIM_LO = 80.6 kΩ 0.625 A
Current Limit, I(LIM_HI) at RILIM_HI = 16.9 kΩ 2.97 A

9.2.2 Detailed Design Procedure

9.2.2.1 Current-Limit Settings

The TPS2543 has two independent current limit settings that are each programmed externally with a resistor. The ILIM_HI setting is programmed with RILIM_HI connected between ILIM_HI and GND. The ILIM_LO setting is programmed with RILIM_LO connected between ILIM_LO and GND. Consult the Device Truth Table (Table 3) to see when each current limit is used. Both settings have the same relation between the current limit and the programming resistor.

RILIM_LO is optional and the ILIM_LO pin may be left unconnected if the following conditions are met:

  1. ILIM_SEL is always set high
  2. Load Detection - Port Power Management is not used
  3. Mouse / Keyboard wake function is not used

If conditions 1 and 2 are met but the mouse / keyboard wake function is also desired, it is recommended to use RILIM_LO < 80.6 kΩ.

Equation 1 programs the typical current limit:

Equation 1. TPS2543 EQ1_lvsba6.gif

RILIM_XX corresponds to either RILIM_HI or RILIM_LO as appropriate.

TPS2543 G018_SLVSBA6.png Figure 40. Typical Current Limit Setting vs Programming Resistor

Many applications require that the current limit meet specific tolerance limits. When designing to these tolerance limits, both the tolerance of the TPS2543 current limit and the tolerance of the external programming resistor must be taken into account. The following equations approximate the TPS2543 minimum / maximum current limits to within a few mA and are appropriate for design purposes. The equations do not constitute part of TI’s published device specifications for purposes of TI’s product warranty. These equations assume an ideal - no variation - external programming resistor. To take resistor tolerance into account, first determine the minimum / maximum resistor values based on its tolerance specifications and use these values in the equations. Because of the inverse relation between the current limit and the programming resistor, use the maximum resistor value in the IOS_min equation and the minimum resistor value in the IOS_max equation.

Equation 2. TPS2543 EQ2_lvsba6.gif
Equation 3. TPS2543 EQ3_lvsba6.gif
TPS2543 G019_SLVSBA6.png Figure 41. Current Limit Setting vs Programming Resistor
TPS2543 G020_SLVSBA6.png Figure 42. Current Limit Setting vs Programming Resistor

The traces routing the RILIM_XX resistors should be a sufficiently low resistance as to not affect the current-limit accuracy. The ground connection for the RILIM_XX resistors is also very important. The resistors need to reference back to the TPS2543 GND pin. Follow normal board layout practices to ensure that current flow from other parts of the board does not impact the ground potential between the resistors and the TPS2543 GND pin.

9.2.3 Application Curves

TPS2543 ilim_hi_waveform.gif Figure 43. High-Current Limit
TPS2543 ilim_lo_waveform.gif Figure 44. Low-Current Limit