8.3.1 Standard Downstream Port (SDP) USB 2.0/USB 3.0

An SDP is a traditional USB port that follows USB 2.0/3.0 protocol and supplies a minimum of 500mA/900mA per port. USB 2.0/3.0 communications is supported, and the host controller must be active to allow charging. TPS2543 supports SDP mode in system power state S0 when system is completely powered ON and fully operational. For more details on control pin (CTL1-CTL3) settings to program this state please refer to device truth table.

8.3.2 Charging Downstream Port (CDP)

A CDP is a USB port that follows USB BC1.2 and supplies a minimum of 1.5A per port. It provides power and meets USB 2.0 requirements for device enumeration. USB 2.0 communications is supported, and the host controller must be active to allow charging. What separates a CDP from an SDP is the host-charge handshaking logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2 client device and allows for additional current draw by the client device.

The CDP hand-shaking process is done in two steps. During step one the portable equipment outputs a nominal 0.6V output on its D+ line and reads the voltage input on its D- line. The portable device concludes it is connected to an SDP if the voltage is less than the nominal data detect voltage of 0.3 V. The portable device concludes that it is connected to a Charging Port if the D- voltage is greater than the nominal data detect voltage of 0.3V and optionally less than 0.8 V.

The second step is necessary for portable equipment to determine if it is connected to CDP or DCP. The portable device outputs a nominal 0.6 V output on its D- line and reads the voltage input on its D+ line. The portable device concludes it is connected to a CDP if the data line being read remains less than the nominal data detect voltage of 0.3V. The portable device concludes it is connected to a DCP if the data line being read is greater than the nominal data detect voltage of 0.3 V.

TPS2543 supports CDP mode in system power state S0 when system is completely powered ON and fully operational. For more details on control pin (CTL1-CTL3) settings to program this state please refer to device truth table.

8.3.3 Dedicated Charging Port (DCP)

A DCP only provides power but does not support data connection to an upstream port. As shown in following sections, a DCP is identified by the electrical characteristics of its data lines. The TPS2543 emulates DCP in two charging states, namely DCP Forced and DCP Auto as shown in Figure 28. In DCP Forced state the device will support one of the two DCP charging schemes, namely Divider1 or Shorted. In the DCP Auto state, the device charge detection state machine is activated to selectively implement charging schemes involved with the Shorted, Divider1 and Divider2 modes. Shorted DCP mode complies with BC1.2 and Chinese Telecommunications Industry Standard YD/T 1591-2009, while the Divider mode is employed to charge devices that do not comply with BC1.2 DCP standard.

8.3.3.1 DCP BC1.2 and YD/T 1591-2009

Both standards define that the D+ and D- data lines should be shorted together with a maximum series impedance of 200 Ω. This is shown in Figure 28.

Figure 28. DCP Supporting BC1.2/YD/T 1591-2009

8.3.3.2 DCP Divider Charging Scheme

There are two Divider charging scheme supported by the device, Divider1 and Divider2 as shown in Figure 29 and Figure 30. In Divider1 charging scheme the device applies 2 V and 2.7 V to D+ and D- data line respectively. This is reversed in Divider2 mode.

Figure 29. DCP Divider1 Charging Scheme

spacer

Figure 30. Divider2 Charging Scheme

8.3.4 Wake on USB Feature (Mouse/Keyboard Wake Feature)

8.3.4.3 USB Slow-Speed Device Recognition and Operation

TPS2543 is capable of detecting LS device attachment when TPS2543 is in SDP or CDP mode. Per USB spec when no device is attached, the D+ and D- lines are near ground level. When a low speed compliant device is attached to the TPS2543 charging port, D- line will be pulled high in its idle state (mouse/keyboard not activated). However when a FS device is attached the opposite is true in its idle state, that is, D+ is pulled high and D- remains at ground level.

When a low speed compliant device is attached to the TPS2543, charging port D- line will be pulled high in its idle state (mouse/keyboard not activated). TPS2543 will monitor D- data line continuously. Since TPS2543 does not monitor D+ line it cannot detect the attachment of a FS device. When TPS2543 is in CDP/SDP mode and system is commanded to go to sleep state, the device CTL setting is also changed. Assuming it is changed to DCP/Auto, 011, having previously detected a low speed HID attachment the device will simply ignore the command to go to DCP/Auto mode and stay in CDP/SDP state to support wake on mouse function. When the USB low speed HID is activated (clicked) while system is in S3 (sleep) mode the high speed switch within the TPS2543 allows the transfer of signal from the LS HID device to the USB host. The USB host subsequently wakes the system and changes CTL setting of the TPS2543 back to CDP/SDP state. Activating (clicking) the low speed device makes the D- data line go back low momentarily, this triggers an internal timer within the TPS2543 to count down. If after ~64 ms the CTL lines are still set at 011 (DCP/Auto) the device will immediately switch to DCP/Auto mode and disconnect the mouse from the host. To prevent this, the CTL setting must be made in less then 64 ms after HID device activation otherwise mouse/KB function will be lost.

Figure 31. Mouse Wake from Sleep Scope Plot

8.3.5 Load Detect

TPS2543 offers system designers unique power management strategy not available in the industry from similar devices. There are two power management schemes supported by the TPS2543 via the STATUS pin, they are:

1. Power Wake (PW)
2. Port Power Management (PPM)

Either feature may be implemented in a system depending on power savings goals for the system. In general Power Wake feature is used mainly in mobile systems like a notebook where it is imperative to save battery power when system is in deep sleep (S4/S5) state. On the other hand Port Power Management feature would be implemented where multiple charging ports are supported in the same system and system power rating is not capable of supporting high current charging on multiple ports simultaneously.

8.3.6 Power Wake

Goal of power wake feature is to save system power when system is in S4/S5 state. In S4/S5 state system is in deep sleep and typically running of the battery; so every “mW” in system power savings will translate to extending battery life. In this state the TPS2543 will monitor charging current at the OUT pin and provide a mechanism via the STATUS pin to switch out the high power DC-DC controller and switch in a low power LDO when charging current requirement is <45 mA (typ). This would be the case when no peripheral device is connected at the charging port or if a device has attained its full battery charge and draws <45 mA.. Power wake flow chart and description is shown in Figure 32.

Figure 32. Power Wake Flow Chart

8.3.6.1 Implementing Power Wake in Notebook System

An implementation of power wake in notebook platforms with the TPS2543 is shown in Figure 33 to Figure 35. Power wake function is used to select between a high power DC-DC converter and low power LDO (100mA) based on charging requirements. System power saving is achieved when under no charging conditions (the connected device is fully charged or no device is connected) the DC-DC converter is turned-off (to save power since it is less efficient in low power operating region) and the low power LDO supplies standby power to the charging port.

Power wake is activated in S4/S5 mode (0011 setting, see device truth table), TPS2543 is charging connected device as shown in Figure 33, STATUS is pulled LO (Case 1) which switches-out the LDO and switches-in the DC-DC converter to handle high current charging.

Figure 33. Case 1: System in S4/S5, Device Charging

As shown in Case 2A and Case 2B, when connected device is fully charged or gets disconnected from the charging port, the charging current will fall. If charging current falls to <45mA and stays below this threshold for over 15s, TPS2543 automatically sets a 55 mA internal current limit and STATUS is de-asserted (pulled HI). As shown in Case 2A and Case 2B. This results in DC-DC converter turning off and the LDO turning on. Current limit of 55 mA is set to prevent the low power LDO output voltage from collapsing in case there is a spike in current draw due to device attachment or other activity such as display panel LED turning ON in connected device.

Following Power Wake flow chart (Figure 32) when a device is attached and draws >55 mA of charging current the TPS2543 hits its internal current limit. This will trigger the device to assert STATUS (LO) and turn on the DC-DC converter and turn off the LDO. TPS2543 discharges OUT for >330 ms (typical) to allow the main power supply to turn on. After the discharge the device will turn back on with current limit set by ILIM_HI
(Case 1)

Figure 34. Case 2A: System in S4/S5, No Device Attached

spacer

Figure 35. Case 2B: System in S4/S5, Attached Device Fully Charged

8.3.7 Port Power Management (PPM)

PPM is the intelligent and dynamic allocation of power. It is for systems that have multiple charging ports but cannot power them all simultaneously. Goal of this feature are:

1. Enhances user experience since user does not have to search for charging port
2. Power supply only has to be designed for a reasonable charging load

Initially all ports are allowed to broadcast high current charging, charging current limit is based on ILIM_HI resistor setting. System monitors STATUS to see when high current loads are present. Once allowed number of ports assert STATUS, remaining ports are toggled to a non-charging port. Non-charging ports are SDP ports with current limit based on ILIM_LO. TPS2543 allows for a system to toggle between charging and non-charging ports either with an OUT discharge or without an OUT discharge.

Figure 36. Implementing Port Power Management in a System Supporting Two Charging Ports

8.3.8 Over-Current Protection

When an over-current condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Two possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before VIN has been applied. The TPS2543 senses the short and immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload occurs, high currents may flow for nominally one to two microseconds before the current-limit circuit can react. The device operates in constant-current mode after the current-limit circuit has responded. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting. The device will remain off until the junction temperature cools approximately 20°C and will then re-start. The device will continue to cycle on/off until the over-current condition is removed.

8.3.9 FAULT Response

The FAULT open-drain output is asserted (active low) during an over-temperature or current limit condition. The output remains asserted until the fault condition is removed. The TPS2543 is designed to eliminate false FAULT reporting by using an internal deglitch circuit for current limit conditions without the need for external circuitry. This ensures that FAULT is not accidentally asserted due to normal operation such as starting into a heavy capacitive load. Over-temperature conditions are not deglitched and assert the FAULT signal immediately.

8.3.10 Undervoltage Lockout (UVLO)

The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turn-on threshold. Built-in hysteresis prevents unwanted oscillations on the output due to input voltage drop from large current surges.

8.3.11 Thermal Sense

The TPS2543 protects itself with two independent thermal sensing circuits that monitor the operating temperature of the power distribution switch and disables operation if the temperature exceeds recommended operating conditions. The device operates in constant-current mode during an over-current condition, which increases the voltage drop across power switch. The power dissipation in the package is proportional to the voltage drop across the power switch, so the junction temperature rises during an over-current condition. The first thermal sensor turns off the power switch when the die temperature exceeds 135°C and the part is in current limit. The second thermal sensor turns off the power switch when the die temperature exceeds 155°C regardless of whether the power switch is in current limit. Hysteresis is built into both thermal sensors, and the switch turns on after the device has cooled by approximately 20°C. The switch continues to cycle off and on until the fault is removed. The open-drain false reporting output FAULT is asserted (active low) during an over-temperature shutdown condition.

spacer

Table 1. Operating Modes

8.4.1 DCP Auto Mode

As mentioned above the TPS2543 integrates an auto-detect state machine that supports all the above DCP charging schemes. It starts in Divider1 scheme, however if a BC1.2 or YD/T 1591-2009 compliant device is attached, the TPS2543 responds by discharging OUT, turning back on the power switch and then moving to BC1.2 DCP mode. It then stays in that mode until the device releases the data line, in which case it goes back to Divider1 scheme. When a Divider1 compliant device is attached the TPS2543 will stay in Divider1 state.

Also, the TPS2543 will automatically switch between the Divider1 and Divider2 schemes based on charging current drawn by the connected device. Initially the device will set the data lines to Divider1 scheme. If charging current of >750 mA is measured by the TPS2543, it discharges and then switches to Divider2 scheme and test to see if the peripheral device will still charge at a high current. If it does then it stays in Divider2 scheme otherwise it performs OUT discharge and will revert to Divider1 scheme.

Figure 37. DCP Auto Mode

8.4.2 DCP Forced Shorted / DCP Forced Divider1

In this mode the device is permanently set to one of the DCP schemes (BC1.2/ YD/T 1591-2009 or Divider1) as commanded by its control pin setting per device truth table.

8.4.3 High-Bandwidth Data Line Switch

The TPS2543 passes the D+ and D- data lines through the device to enable monitoring and handshaking while supporting charging operation. A wide bandwidth signal switch is used, allowing data to pass through the device without corrupting signal integrity. The data line switches are turned on in any of CDP or SDP operating modes. The EN input also needs to be at logic High for the data line switches to be enabled.

Table 2 can be used as an aid to program the TPS2543 per system states however not restricted to below settings only.

8.4.4 Device Truth Table (TT)

Device TT lists all valid bias combinations for the three control pins CTL1-3 and ILIM_SEL pin and their corresponding charging mode. It is important to note that the TT purposely omits matching charging modes of the TPS2543 with global power states (S0-S5) as device is agnostic to system power states. The TPS2543 monitors its CTL inputs and will transition to whatever charging state it is commanded to go to (except when LS HID device is detected). For example if sleep charging is desired when system is in standby or hibernate state then user must set TPS2543 CTL pins to correspond to DCP_Auto charging mode per below table. When system is put back to operation mode then set control pins to correspond to SDP or CDP mode and so on.