JAJSEJ1 データシート

JAJSEJ1B november 2017 – july 2020 TPS254900A-Q1

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

RVC|20

サーマルパッド・メカニカル・データ

RVC|20
- QFND186C

発注情報

6.5 Electrical Characteristics

Unless otherwise noted, –40°C ≤ T_J ≤ 125°C and 4.5 V ≤ V_(IN) ≤ 6.5 V, V_(EN) = V_(CTL1) = V_(CTL2) = V_(IN), R_(FAULT) = R_(STATUS) = 10 kΩ, R_(IMON) = 2.55 kΩ, R_{(ILIM_HI)} = 19.1 kΩ, R_{(ILIM_LO)} = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OUT – POWER SWITCH
r_DS(on)	On-resistance⁽¹⁾	T_J = 25°C		45	55	mΩ
		–40°C ≤ T_J ≤ 85°C		45	69
		–40°C ≤T_J ≤ 125°C		45	77
I_lkg	Reverse leakage current	V_OUT = 6.5 V, V_IN = V_EN = 0 V, –40°C ≤ T_J ≤ 85°C, measure I_(IN)		0.01	2	µA
OUT – DISCHARGE
R_(DCHG)	Discharge resistance (mode change)		400	500	630	Ω
CTL1, CTL2, EN, OVP_SEL INPUTS
	Input pin rising logic threshold voltage		0.8	1.35	2	V
	Input pin falling logic threshold voltage		0.7	1.15	1.65	V
	Hysteresis⁽²⁾			200		mV
	Input current	Pin voltage = 0 V or 6.5 V	–1		1	µA
CURRENT LIMIT
I_OS	OUT short-circuit current limit	R_{(ILIM_LO)} = 210 kΩ	190	240	290	mA
		R_{(ILIM_LO)} = 80.6 kΩ	555	620	680
		R_{(ILIM_LO)} = 21.5 kΩ	2145	2300	2460
		R_{(ILIM_LO)} = 19.1 kΩ	2420	2590	2760
		R_{(ILIM_HI)} = 18.2 kΩ	2545	2720	2895
		R_{(ILIM_HI)} = 14.3 kΩ	3240	3455	3670
		R_{(ILIM_HI)} = 13.5 kΩ	3435	3660	3890
		R_{(ILIM_HI)} = 11.8 kΩ	3930	4180	4440
		R_{(ILIM_HI)} = 9.6 kΩ	4835	5135	5450
		R_{(ILIM_HI)} shorted to GND	5000	6500	8000
SUPPLY CURRENT
I_{(IN_OFF)}	Disabled IN supply current	V_(EN) = 0 V, V_(OUT) = 0 V, –40°C ≤ T_J ≤ 85°C, no 5.1-kΩ resistor (open) between BIAS and OUT		0.1	5	µA
I_{(IN_ON)}	Enabled IN supply current	SDP mode (CTL1, CTL2 = 0, 1)		170	250	µA
		CDP mode (CTL1, CTL2 = 1, 1)		200	280
		Client mode (CTL1, CTL2 = 0, 0)		120	210
UNDERVOLTAGE LOCKOUT, IN
V_(UVLO)	UVLO threshold voltage	IN rising	3.9	4.1	4.3	V
V_(UVLO)	UVLO threshold voltage	IN falling	3.3	3.5	3.7	V
FAULT
	Output low voltage	I_(FAULT) = 1 mA			100	mV
	Off-state leakage	V_(FAULT) = 6.5 V			2	µA
STATUS
	Output low voltage	I_(STATUS) = 1 mA			100	mV
	Off-state leakage	V_(STATUS) = 6.5 V			2	µA
THERMAL SHUTDOWN
T_(OTSD2)	Thermal shutdown threshold		155			°C
T_(OTSD1)	Thermal shutdown threshold in current-limit		135			°C
	Hysteresis⁽³⁾			20		°C
LOAD DETECT (V_CTL1 = V_CTL2 = V_IN)
I_(LD)	I_OUT load detection threshold	R_{(ILIM_LO)} = 80.6 kΩ, rising load current	585	650	715	mA
	Hysteresis⁽³⁾			50		mA
DM_IN AND DP_IN OVERVOLTAGE PROTECTION
V_{(OV_Data)}	Protection trip threshold	DP_IN and DM_IN rising	3.3	3.9	4.15	V
	Hysteresis⁽³⁾			100		mV
R_{(DCHG_Data)}	Discharge resistor after OVP(2)	DP_IN = DM_IN = 18 V, IN = 5 V or 0 V		200		kΩ
		DP_IN = DM_IN = 5 V, IN = 5 V		370
		DP_IN = DM_IN = 5 V, IN = 0		390
OUT OVERVOLTAGE PROTECTION
V_{(OV_OUT_LOW)}	Protection trip threshold	OUT rising	5.65	6	6.35	V
	Hysteresis⁽³⁾			90		mV
V_{(OV_OUT_HIGH)}	Protection trip threshold	OUT rising	6.6	6.95	7.3	V
	Hysteresis⁽³⁾			130		mV
R_{(DCHG_OUT)}	Discharge resistor	OUT = 18 V, IN = 5 V		55	85	kΩ
R_{(DCHG_OUT)}	Discharge resistor	OUT = 18 V, IN = 0		80	120	kΩ
CABLE COMPENSATION
I_(CS)	Sink current	Load = 3.2 A, 2.5 V ≤ V_(CS) ≤ 6.5 V	250	262	275	µA
		Load = 3 A, 2.5 V ≤ V_(CS) ≤ 6.5 V	234	246	258
		Load = 2.4 A, 2.5 V ≤ V_(CS) ≤ 6.5 V	187	197	207
		Load = 2.1 A, 2.5 V ≤ V_(CS) ≤ 6.5 V	163	172	181
		Load = 1 A, 2.5 V ≤ V_(CS) ≤ 6.5 V	77	82	87
CURRENT MONITOR OUTPUT (IMON)
I_(IMON)	Source current	Load = 3.2 A, 0 ≤ V_(IMON) ≤ 2.5 V	306	333	359	µA
		Load = 3 A, 0 ≤ V_(IMON) ≤ 2.5 V	287	312	337
		Load = 2.4 A, 0 ≤ V_(IMON) ≤ 2.5 V	230	250	270
		Load = 2.1 A, 0 ≤ V_(IMON) ≤ 2.5 V	201	218	235
		Load = 1 A, 0 ≤ V_(IMON) ≤ 2.5 V	94	104	114
		Load = 0.5 A, 0 ≤ V_(IMON) ≤ 2.5 V	44	52	60
HIGH-BANDWIDTH ANALOG SWITCH
R_{(HS_ON)}	DP and DM switch on-resistance	V_{(DP_OUT)} = V_{(DM_OUT)} = 0 V, I_{(DP_IN)} = I_{(DM_IN)} = 30 mA		3.2	6.5	Ω
R_{(HS_ON)}	DP and DM switch on-resistance	V_{(DP_OUT)} = V_{(DM_OUT)} = 2.4 V, I_{(DP_IN)} = I_{(DM_IN)} = –15 mA		3.8	7.6	Ω
\|ΔR_{(HS_ON)}\|	Switch resistance mismatch between DP and DM channels	V_{(DP_OUT)} = V_{(DM_OUT)} = 0 V, I_{(DP_IN)} = I_{(DM_IN)} = 30 mA		0.05	0.15	Ω
\|ΔR_{(HS_ON)}\|	Switch resistance mismatch between DP and DM channels	V_{(DP_OUT)} = V_{(DM_OUT)} = 2.4 V, I_{(DP_IN)} = I_{(DM_IN)} = –15 mA		0.05	0.15	Ω
C_{(IO_OFF)}	DP and DM switch off-state capacitance⁽⁴⁾	V_EN = 0 V, V_{(DP_IN)} = V_{(DM_IN)} = 0.3 V, Vac = 0.03 V_PP, f = 1 MHz		8.8		pF
C_{(IO_ON)}	DP and DM switch on-state capacitance⁽⁴⁾	V_{(DP_IN)} = V_{(DM_IN)} = 0.3 V, Vac = 0.03 V_PP, f = 1 MHz		10.9		pF
	Off-state isolation(3)	V_(EN) = 0 V, f = 250 MHz		8		dB
	On-state cross-channel isolation⁽⁴⁾	f = 250 MHz		30		dB
I_lkg(OFF)	Off-state leakage current	V_EN = 0 V, V_{(DP_IN)} = V_{(DM_IN)} = 3.6 V, V_{(DP_OUT)} = V_{(DM_OUT)} = 0 V, measure I_{(DP_OUT)} and I_{(DM_OUT)}		0.1	1.5	µA
BW	Bandwidth (–3 dB)⁽⁴⁾	R_(L) = 50 Ω		940		MHz
CHARGING DOWNSTREAM PORT DETECT
V_{(DM_SRC)}	DM_IN CDP output voltage	V_{(DP_IN)} = 0.6 V, –250 µA < I_{(DM_IN)} < 0 µA	0.5	0.6	0.7	V
V_{(DAT_REF)}	DP_IN rising lower window threshold for V_{(DM_SRC)} activation		0.36		0.4	V
	Hysteresis⁽⁴⁾			50		mV
V_{(LGC_SRC)}	DP_IN rising upper window threshold for VDM_SRC de-activation		0.8		0.88	V
V_{(LGC_SRC_HYS)}	Hysteresis⁽⁴⁾			100		mV
I_{(DP_SINK)}	DP_IN sink current	V_{(DP_IN)} = 0.6 V	40	75	100	µA

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account separately.

(2) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's product warranty.

(3) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's product warranty.

(4) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's product warranty.