JAJSRT9
October 2023
TPS25730
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.1.1
TPS25730D and TPS25730S - Absolute Maximum Ratings
6.1.2
TPS25730D - Absolute Maximum Ratings
6.1.3
TPS25730S - Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.3.1
TPS25730D - Recommended Operating Conditions
6.3.2
TPS25730S - Recommended Operating Conditions
6.4
Recommended Capacitance
6.5
Thermal Information
6.5.1
TPS25730D - Thermal Information
6.5.2
TPS25730S - Thermal Information
6.6
Power Supply Characteristics
6.7
Power Consumption
6.8
PPHV Power Switch Characteristics - TPS25730D
6.9
PP_EXT Power Switch Characteristics - TPS25730S
6.10
Power Path Supervisory
6.11
CC Cable Detection Parameters
6.12
CC PHY Parameters
6.13
Thermal Shutdown Characteristics
6.14
ADC Characteristics
6.15
Input/Output (I/O) Characteristics
6.16
I2C Requirements and Characteristics
6.17
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
USB-PD Physical Layer
8.3.1.1
USB-PD Encoding and Signaling
8.3.1.2
USB-PD Bi-Phase Marked Coding
8.3.1.3
USB-PD BMC Transmitter
8.3.1.4
USB-PD BMC Receiver
8.3.1.5
Squelch Receiver
8.3.2
Power Management
8.3.2.1
Power-On And Supervisory Functions
8.3.2.2
VBUS LDO
8.3.3
Power Paths
8.3.3.1
TPS25730D Internal Sink Path
8.3.3.2
TPS25730S - External Sink Path Control PP_EXT
8.3.4
Cable Plug and Orientation Detection
8.3.5
Overvoltage Protection (CC1, CC2)
8.3.6
Default Behavior Configuration (ADCIN1, ADCIN2)
8.3.7
ADC
8.3.8
Digital Interfaces
8.3.9
Digital Core
8.3.10
I2C Interface
8.3.10.1
I2C Interface Description
8.3.10.1.1
I2C Clock Stretching
8.3.10.1.2
Unique Address Interface
8.3.10.1.3
Pin Strapping to Configure Default Behavior
8.3.11
Minimum Voltage Configuration
8.3.12
Maximum Voltage Configuration
8.3.13
Sink Current Configuration
8.3.14
Autonegotiate Sink Minimum Power
8.3.15
Extended Sink Capabilities Power Delivery Power
8.4
Device Functional Modes
8.4.1
Power States
8.5
Schottky for Current Surge Protection
8.6
Thermal Shutdown
9
Application and Implementation
9.1
Application Information
9.1.1
Supported Sink Power Configurations
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.3.1
3.3-V Power
9.3.1.1
VIN_3V3 Input Switch
9.3.2
1.5-V Power
9.3.3
Recommended Supply Load Capacitance
9.4
Layout
9.4.1
TPS25730D - Layout
9.4.1.1
Layout Guidelines
9.4.1.1.1
Top Placement and Bottom Component Placement and Layout
9.4.1.2
Layout Example
9.4.1.3
Component Placement
9.4.1.4
Routing VBUS, VIN_3V3, LDO_3V3, LDO_1V5
9.4.1.5
Routing CC and GPIO
9.4.2
TPS25730S - Layout
9.4.2.1
Layout Guidelines
9.4.2.1.1
Top Placement and Bottom Component Placement and Layout
9.4.2.2
Layout Example
9.4.2.3
Component Placement
9.4.2.4
Routing VBUS, PPHV, VIN_3V3, LDO_3V3, LDO_1V5
9.4.2.5
Routing CC and GPIO
10
Device and Documentation Support
10.1
Device Support
10.1.1
サード・パーティ製品に関する免責事項
10.2
Documentation Support
10.2.1
Related Documentation
10.3
ドキュメントの更新通知を受け取る方法
10.4
サポート・リソース
10.5
Trademarks
10.6
静電気放電に関する注意事項
10.7
用語集
11
Revision History
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
REF|38
MPQF652A
RSM|32
MPQF195B
サーマルパッド・メカニカル・データ
RSM|32
QFND112H
発注情報
jajsrt9_oa
jajsrt9_pm
6
Specifications