JAJSRT9 October   2023 TPS25730

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
      1. 6.1.1 TPS25730D and TPS25730S - Absolute Maximum Ratings
      2. 6.1.2 TPS25730D - Absolute Maximum Ratings
      3. 6.1.3 TPS25730S - Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
      1. 6.3.1 TPS25730D - Recommended Operating Conditions
      2. 6.3.2 TPS25730S - Recommended Operating Conditions
    4. 6.4  Recommended Capacitance
    5. 6.5  Thermal Information
      1. 6.5.1 TPS25730D - Thermal Information
      2. 6.5.2 TPS25730S - Thermal Information
    6. 6.6  Power Supply Characteristics
    7. 6.7  Power Consumption
    8. 6.8  PPHV Power Switch Characteristics - TPS25730D
    9. 6.9  PP_EXT Power Switch Characteristics - TPS25730S
    10. 6.10 Power Path Supervisory
    11. 6.11 CC Cable Detection Parameters
    12. 6.12 CC PHY Parameters
    13. 6.13 Thermal Shutdown Characteristics
    14. 6.14 ADC Characteristics
    15. 6.15 Input/Output (I/O) Characteristics
    16. 6.16 I2C Requirements and Characteristics
    17. 6.17 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. 8.3.1.1 USB-PD Encoding and Signaling
        2. 8.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.1.3 USB-PD BMC Transmitter
        4. 8.3.1.4 USB-PD BMC Receiver
        5. 8.3.1.5 Squelch Receiver
      2. 8.3.2  Power Management
        1. 8.3.2.1 Power-On And Supervisory Functions
        2. 8.3.2.2 VBUS LDO
      3. 8.3.3  Power Paths
        1. 8.3.3.1 TPS25730D Internal Sink Path
        2. 8.3.3.2 TPS25730S - External Sink Path Control PP_EXT
      4. 8.3.4  Cable Plug and Orientation Detection
      5. 8.3.5  Overvoltage Protection (CC1, CC2)
      6. 8.3.6  Default Behavior Configuration (ADCIN1, ADCIN2)
      7. 8.3.7  ADC
      8. 8.3.8  Digital Interfaces
      9. 8.3.9  Digital Core
      10. 8.3.10 I2C Interface
        1. 8.3.10.1 I2C Interface Description
          1. 8.3.10.1.1 I2C Clock Stretching
          2. 8.3.10.1.2 Unique Address Interface
          3. 8.3.10.1.3 Pin Strapping to Configure Default Behavior
      11. 8.3.11 Minimum Voltage Configuration
      12. 8.3.12 Maximum Voltage Configuration
      13. 8.3.13 Sink Current Configuration
      14. 8.3.14 Autonegotiate Sink Minimum Power
      15. 8.3.15 Extended Sink Capabilities Power Delivery Power
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power States
    5. 8.5 Schottky for Current Surge Protection
    6. 8.6 Thermal Shutdown
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Supported Sink Power Configurations
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 3.3-V Power
        1. 9.3.1.1 VIN_3V3 Input Switch
      2. 9.3.2 1.5-V Power
      3. 9.3.3 Recommended Supply Load Capacitance
    4. 9.4 Layout
      1. 9.4.1 TPS25730D - Layout
        1. 9.4.1.1 Layout Guidelines
          1. 9.4.1.1.1 Top Placement and Bottom Component Placement and Layout
        2. 9.4.1.2 Layout Example
        3. 9.4.1.3 Component Placement
        4. 9.4.1.4 Routing VBUS, VIN_3V3, LDO_3V3, LDO_1V5
        5. 9.4.1.5 Routing CC and GPIO
      2. 9.4.2 TPS25730S - Layout
        1. 9.4.2.1 Layout Guidelines
          1. 9.4.2.1.1 Top Placement and Bottom Component Placement and Layout
        2. 9.4.2.2 Layout Example
        3. 9.4.2.3 Component Placement
        4. 9.4.2.4 Routing VBUS, PPHV, VIN_3V3, LDO_3V3, LDO_1V5
        5. 9.4.2.5 Routing CC and GPIO
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-20231016-SS0I-76LL-97KB-BRGTBM94ZJD8-low.svg Figure 5-1 Top View of the TPS25730D 38-pin QFN Package

GUID-20231016-SS0I-NCGP-KVVR-TGS7NZ3V9FJK-low.svg Figure 5-2 Top View of the TPS25730S 32-pin QFN Package

Table 5-1 TPS25730D Pin Functions
PINTYPE(1)RESETDESCRIPTION
NAMENO.
ADCIN12IHi-ZConfiguration Input. Connect to a resistor divider to LDO_3V3.
ADCIN23IHi-ZConfiguration Input. Connect to a resistor divider to LDO_3V3.
CC128I/OHi-ZI/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy).
CC229I/OHi-ZI/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy).
GND11, 12, 14, 16, 17, 31, 34, 35——Ground. Connect to ground plane.
ADCIN35IHi-ZConfiguration Input. Connect to a resistor divider to LDO_3V3.
CAP_MIS6OHi-ZOpen Drain Output, Capability Mismatch indicator. Toggled Output: Capability Mismatch in negotiated PD contract, No Toggled Output: No Capability Mismatch in negotiated PD contract.
ADCIN47IHi-ZConfiguration Input. Connect to a resistor divider to LDO_3V3.
SINK_EN19OHi-ZOpen Drain Output, Sink path enabled indicator, may be used to control an external load switch. 0: Sink Path Enabled, 1: Sink Path Disabled
RESERVED26, 27, 36IHi-ZTie to ground or LDO_3V3
PLUG_EVENT37OHi-ZOpen Drain Output, 1: Connection Present 0: No Connection Present
I2Ct_SCL9IHi-ZI2C target serial clock input. Tie to pullup voltage through a resistor. May be grounded if unused.
I2Ct_SDA8I/OHi-ZI2C target serial data. Open-drain input/output. Tie to pullup voltage through a resistor. May be grounded if unused.
DBG_ACC10OHi-ZOpen Drain Output, Debug Accessory attached Rp/Rp or Rd/Rd. 1: Debug Accessory Present, 0: No Debug Accessory Present
PLUG_FLIP13OHi-ZOpen Drain Output, Cable plug orientation indicator. 1: CC2 connected (upside-down), 0: CC1 connected (upside-up)
FAULT_IN18IHi-ZFault Input to disconnect from the port. When powered from VBUS this causes the PD controller to lose power when VBUS is removed. 0: Disconnect from port, 1: Maintain connection - no fault
LDO_1V54O—Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. This pin cannot source current to external circuits.
LDO_3V31O—Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with capacitance CLDO_3V3 to GND.
DRAIN15, 30N/A—Connects to drain of internal FET.
PPHV20, 21, 22I/OHigh-voltage sinking node in the system.
VBUS_IN23, 24, 25

I/O

5-V to 20-V input.
VBUS32, 33OVBUS input to LDO. Bypass with capacitance CVBUS to GND.
VIN_3V338I—Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.
(1) I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output
Table 5-2 TPS25730S Pin Functions
PINTYPE(1)RESETDESCRIPTION
NAMENO.
ADCIN12IHi-ZConfiguration Input. Connect to a resistor divider to LDO_3V3.
ADCIN23IHi-ZConfiguration Input. Connect to a resistor divider to LDO_3V3.
CC124I/OHi-ZI/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy).
CC225I/OHi-ZI/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy).
GATE_VSYS 20 O Hi-Z Connect to the N-ch MOSFET that has source tied to VSYS
GATE_VBUS 21 O Hi-Z Connect to the N-ch MOSFET that has source tied to VBUS
GND11, 12, 14, 15, 16, 28, 29——Ground. Connect to ground plane.
ADCIN35IHi-ZConfiguration Input. Connect to a resistor divider to LDO_3V3.
CAP_MIS6OHi-ZOpen Drain Output, Capability Mismatch indicator. Toggled Output: Capability Mismatch in negotiated PD contract, No Toggled Output: No Capability Mismatch in negotiated PD contract.
ADCIN47IHi-ZConfiguration Input. Connect to a resistor divider to LDO_3V3.
SINK_EN18OHi-ZOpen Drain Output, Sink path enabled indicator, may be used to control an external load switch. 0: Sink Path Enabled, 1: Sink Path Disabled
RESERVED22, 23, 30IHi-ZTie to ground or LDO_3V3
PLUG_EVENT31OHi-ZOpen Drain Output, 1: Connection Present 0: No Connection Present
I2Ct_SCL9IHi-ZI2C target serial clock input. Tie to pullup voltage through a resistor. May be grounded if unused.
I2Ct_SDA8I/OHi-ZI2C target serial data. Open-drain input/output. Tie to pullup voltage through a resistor. May be grounded if unused.
DBG_ACC10OHi-ZOpen Drain Output, Debug Accessory attached Rp/Rp or Rd/Rd. 1: Debug Accessory Present, 0: No Debug Accessory Present
PLUG_FLIP13OHi-ZOpen Drain Output, Cable plug orientation indicator. 1: CC2 connected (upside-down), 0: CC1 connected (upside-up)
FAULT_IN17IHi-ZFault Input to disconnect from the port. When powered from VBUS this causes the PD controller to lose power when VBUS is removed. 0: Disconnect from port, 1: Maintain connection - no fault
LDO_1V54O—Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. This pin cannot source current to external circuits.
LDO_3V31O—Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with capacitance CLDO_3V3 to GND.
VSYS 19 I — High-voltage sinking node in the system. Used to implement reverse current protection (RCP) for the external sink path controlled by GATE_VSYS.
VBUS26, 27I/O5-V to 20-V input. Bypass with capacitance CVBUS to GND.
VIN_3V332I—Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.
(1) I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output