JAJSRT9 October   2023 TPS25730

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
      1. 6.1.1 TPS25730D and TPS25730S - Absolute Maximum Ratings
      2. 6.1.2 TPS25730D - Absolute Maximum Ratings
      3. 6.1.3 TPS25730S - Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
      1. 6.3.1 TPS25730D - Recommended Operating Conditions
      2. 6.3.2 TPS25730S - Recommended Operating Conditions
    4. 6.4  Recommended Capacitance
    5. 6.5  Thermal Information
      1. 6.5.1 TPS25730D - Thermal Information
      2. 6.5.2 TPS25730S - Thermal Information
    6. 6.6  Power Supply Characteristics
    7. 6.7  Power Consumption
    8. 6.8  PPHV Power Switch Characteristics - TPS25730D
    9. 6.9  PP_EXT Power Switch Characteristics - TPS25730S
    10. 6.10 Power Path Supervisory
    11. 6.11 CC Cable Detection Parameters
    12. 6.12 CC PHY Parameters
    13. 6.13 Thermal Shutdown Characteristics
    14. 6.14 ADC Characteristics
    15. 6.15 Input/Output (I/O) Characteristics
    16. 6.16 I2C Requirements and Characteristics
    17. 6.17 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. 8.3.1.1 USB-PD Encoding and Signaling
        2. 8.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.1.3 USB-PD BMC Transmitter
        4. 8.3.1.4 USB-PD BMC Receiver
        5. 8.3.1.5 Squelch Receiver
      2. 8.3.2  Power Management
        1. 8.3.2.1 Power-On And Supervisory Functions
        2. 8.3.2.2 VBUS LDO
      3. 8.3.3  Power Paths
        1. 8.3.3.1 TPS25730D Internal Sink Path
        2. 8.3.3.2 TPS25730S - External Sink Path Control PP_EXT
      4. 8.3.4  Cable Plug and Orientation Detection
      5. 8.3.5  Overvoltage Protection (CC1, CC2)
      6. 8.3.6  Default Behavior Configuration (ADCIN1, ADCIN2)
      7. 8.3.7  ADC
      8. 8.3.8  Digital Interfaces
      9. 8.3.9  Digital Core
      10. 8.3.10 I2C Interface
        1. 8.3.10.1 I2C Interface Description
          1. 8.3.10.1.1 I2C Clock Stretching
          2. 8.3.10.1.2 Unique Address Interface
          3. 8.3.10.1.3 Pin Strapping to Configure Default Behavior
      11. 8.3.11 Minimum Voltage Configuration
      12. 8.3.12 Maximum Voltage Configuration
      13. 8.3.13 Sink Current Configuration
      14. 8.3.14 Autonegotiate Sink Minimum Power
      15. 8.3.15 Extended Sink Capabilities Power Delivery Power
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power States
    5. 8.5 Schottky for Current Surge Protection
    6. 8.6 Thermal Shutdown
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Supported Sink Power Configurations
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 3.3-V Power
        1. 9.3.1.1 VIN_3V3 Input Switch
      2. 9.3.2 1.5-V Power
      3. 9.3.3 Recommended Supply Load Capacitance
    4. 9.4 Layout
      1. 9.4.1 TPS25730D - Layout
        1. 9.4.1.1 Layout Guidelines
          1. 9.4.1.1.1 Top Placement and Bottom Component Placement and Layout
        2. 9.4.1.2 Layout Example
        3. 9.4.1.3 Component Placement
        4. 9.4.1.4 Routing VBUS, VIN_3V3, LDO_3V3, LDO_1V5
        5. 9.4.1.5 Routing CC and GPIO
      2. 9.4.2 TPS25730S - Layout
        1. 9.4.2.1 Layout Guidelines
          1. 9.4.2.1.1 Top Placement and Bottom Component Placement and Layout
        2. 9.4.2.2 Layout Example
        3. 9.4.2.3 Component Placement
        4. 9.4.2.4 Routing VBUS, PPHV, VIN_3V3, LDO_3V3, LDO_1V5
        5. 9.4.2.5 Routing CC and GPIO
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9 PP_EXT Power Switch Characteristics - TPS25730S

Operating under these conditions unless otherwise noted: , 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
IGATE_ONGate driver sourcing current0 ≤ VGATE_VSYS - VVSYS ≤ 6 V, VVSYS ≤ 22 V, VVBUS > 4 V, measure IGATE_VSYS8.511.5µA
0 ≤ VGATE_VBUS - VVBUS ≤ 6 V, 4 V ≤ VVBUS ≤ 22 V, measure IGATE_VBUS8.511.5µA
VGATE_ONSourcing voltage (ON)0 ≤ VVSYS ≤ 22 V, IGATE_VSYS < 4 µA, measure VGATE_VSYS – VVSYS, VVBUS > 4 V612V
4 V ≤ VVBUS ≤ 22 V, IGATE_VBUS < 4 µA, measure VGATE_VBUS – VVBUS612V
VRCPComparator mode RCP threshold, VVSYS - VVBUS4 V ≤ VVBUS ≤ 22 V, VVIN_3V3  ≤ 3.63 V2610mV
IGATE_OFFSinking strengthNormal turnoff: VVSYS = 5 V, VGATE_VSYS = 6 V, measure IGATE_VSYS13µA
Normal turnoff: VVBUS = VVSYS = 5 V, VGATE_VBUS = 6 V, measure IGATE_VBUS13µA
RGATE_FSDSinking strengthFast turnoff: VVSYS = 5 V, VGATE_VSYS = 6 V, assert PPHV1_FAST_DISABLE, measure RGATE_VSYS85Ω
Fast turnoff: VVBUS = VVSYS = 5 V, VGATE_VBUS = 6 V, assert PPHV1_FAST_DISABLE, measure RGATE_VBUS85Ω
RGATE_OFF_UVLOSinking strength in UVLO (safety)VVIN_3V3 = 0 V, VVBUS = 3.0 V, VGATE_VSYS = 0.1 V,  measure resistance from GATE_VSYS to GND1.5MΩ
SSSoft start slew rate for GATE_VSYS4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 2.83.33.80 V/ms
tGATE_VBUS_OFFTime allowed to disable the external FET via GATE_VBUS in normal shutdown mode.(1)VVBUS = 20 V, QG of external FET = 40 nC or CGATE_VBUS < 3 nF, gate is off when VGATE_VBUS – VVBUS < 1 V4504000µs
tGATE_VBUS_OVPTime allowed to disable the external FET via GATE_VBUS in fast shutdown mode (VOVP4RCP exceeded), this includes the response time of the comparator(1)OVP: VOVP4RCP = setting 57, VVBUS = 20 V initially, then raised to 23 V in 50 ns, QG of external FET = 40 nC or CGATE_VBUS < 3 nF, gate is off when VGATE_VBUS – VVBUS < 1 V35µs
tGATE_VBUS_RCPTime allowed to disable the external FET via GATE_VBUS in fast shutdown mode (VRCP exceeded), this includes the response time of the comparator(1)RCP: VRCP = setting 0, VVBUS = 5 V, VVSYS = 5 V initially, then raised to 5.5 V in 50 ns, QG of external FET = 40 nC or CGATE_VBUS < 3 nF, gate is off when VGATE_VBUS – VVBUS < 1 V12µs
tGATE_VSYS_OFFTime allowed to disable the external FET via GATE_VSYS in normal shutdown mode(1)VVSYS= 20 V, QG of external FET = 40 nC or CGATE_VBUS < 3 nF, gate is off when VGATE_VSYS – VVSYS < 1 V4504000µs
tGATE_VSYS_FSDTime allowed to disable the external FET via GATE_VSYS in fast shutdown mode (OVP)(1)VVBUS = 20 V initially, then raised to 23 V in 50 ns, QG of external FET = 40 nC or CGATE_VBUS < 3 nF, gate is off when VGATE_VSYS – VVSYS < 1 V, rOVP = 10.2520μs
tGATE_VBUS_ONTime to enable GATE_VBUS (1)Measure time from when VGS = 0 V until VGS >3 V, where VGS = VGATE_VBUS – VVBUS 0.252ms
(1) These values depend upon the characteristics of the external N-ch MOSFET. The typical values were measured when Px_GATE_VSYS and Px_GATE_VBUS were used to drive two CSD17571Q2 in common drain back-to-back configuration.